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    GDSII stream out problem

    Hi, I am using Cadence icfb to stream out the GDSII file for the foundry. For some reason, the foundry just gave me a incomplete design kit: the layout of standard cells don't have all the layers. When I finish my layout, the foundry will substitute all the standard cells I used in my design...
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    Any advice on hierarchical layout to avoid DRC violations on top level?

    Hi everyone, when we do a chip layout, usually we do it in a hierarchy way. It means that we do the modules and blocks layout first, then the top layout. But when we do the top layout, the only physical information we have about the sub-modules and blocks is contained in the LEF files, which...
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    what is the difference between LEF file generated from Encounter and Abstract?

    Hi, As far as I know, we can generate a LEF file of a block after place&route using Encounter. After that, we can extract information of the block layout using Abstract, and then generate another LEF file. What's the difference between the two? and which one should we use in top level...
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    What is the notion of "core" in chip physic design?

    Hi, I have a question of floorplan. In top chip layout when we define a core and its dimension in the command "floorplan", does it mean all the cells (IPs, standard cells, analog instances...) should be placed inside? There is only something like power rings, pad rings, wire connections outside...
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    Pad placement rules

    Hi everyone, could you please give me some advice on pad placement, especially for power/ground pads? I know some basic rules like 1. place the pads close to their corresponding pins to simplify routing 2. place VDD or VSS around special pads like refclock, reset for noise shielding what else?
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    problem when adding stripe

    problem when adding stripe :antenna segment Hi everyone, I have a problem when adding stripes in my design. I want to add four vertical stripes. The first one works. The second and third one are shorter than the value I set. The fourth one is cut into two segments. There are warnings like this...
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    How to route two matching signals in Encounter?

    Hi everyone, In my design, I have some special pairs of wires. The two signals in each pair should be totally matching with each other, having the same transmission delay like "differential signals". Is there any commands that I could use as timing constraint or routing options in Encounter? Thanks
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    Qestion: Place and route of 100 identical modules

    Hi everyone, I am doing the layout of a chip, whose main part is a network of 100 identical modules (just like a memory). I have the layout of the module and I put the pins carefully so that the 100 instances can be put next to each other. The communication between neighboring instances are...
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    [SOLVED] set_false_path for static input

    Hi, I have a circuit with two asynchronous clocks, one low frequency clock SCK is for programming the coefficients COEF[19..0] in the instance ISPI at the startup phase. Once the programming process is finished, COEF[19..0] doesnot change any more, the other instance IFILTER cadenced by the...
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    outside control voltage signal precesion

    outside control voltage signal precision Hi, everybody, I have a voltage controlled block in my chip. the control voltage will be generated by a outside device, and tuned manually during chip test. Does anyone know the precision that the outside voltage control signal can achieve normally? thx...

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