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    How to evaluate the performance of TDC?

    Thank KlausST very much. Your comment is really good for me after my chip is fabricated. Currently, I just wonder how to simulate ENOB, INL/DNL of TDC. So do you have any suggestion for simulation? Best regards.
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    How to evaluate the performance of TDC?

    Hi everyone, I've just finished design TDC. I check each output code in very small period of time to find out it is correct or not, surely that is not the way, but I don't know what's the best way to evaluate the performance of my design. Could you please give me any suggestions about evaluate...
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    Error: Internal Error: code [1003] in new analysis.

    Hi everyone, I simulated my circuit using Hspice and I got the error "Error: Internal Error: code [1003] in new analysis." The problem is I run 2 simulation, one-ckt1 can be finished and another-ckt2 got that error, and I tried to simulate ckt2 again, but it still was error. I really don't...
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    reference voltage of the bandgap reference circuit by using 0.13um CMOS silterra tech

    Hi hujiaomianhao, Totally Yes! In the first simulation, with Vdd = 1.8V, it can run very well. And in second one, I try it with Vdd=1.2V, it also has good performance! ^_^
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    SRAM design reference

    Hi madalin1990, I have just finished SRAM project at university. I followed the attached report. And finally, it meets specifications :grin: Hope this help!
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    ICMR of an NMOS input Op-Amp

    Hi Senan, I got the simulation result based on the book:"Analysis and Design of Analog Integrated Circuit" 4th Edition. Also, as you see the definition of ICMR, it seems does not relate to Vout, just only Vin (if that, you do not need to plot Vout in graph). But ICMR is affected by output swing...
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    ICMR of an NMOS input Op-Amp

    Hi senan, Simulate OPAMP with buffer feedback configuration. And then run Vin from 0v to Vdd: The simulation result will be looked like this: Have fun!
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    How to avoid kickback noise in a dynamic comparator?

    Hi helna! Actually, kickback noise can make offset to your circuit as u mentioned. To remove it, you can read some techniques in some following papers (i think they are the best for your circuit): 1. Kickback Noise Reduction Techniques for CMOS Latched Comparators - Pedro M. Figueiredo. 2. A...
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    Help in education in electronics

    Hi dsaint, I have already learned 6.002x Circuits and Electronics online course offered by MIT. Here is the link: **broken link removed** I think this course is pretty nice to motivate your learning process. Hope this help!
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    Question's about the average energy in capacitor switching procedure SAR ADC.

    Hi, I read the paper:" A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure" and i do not understand how the authors get the average energy in picture (a): At the first conversion, why the energy is C*Vref^2 and 5*C*Vref^2, and so on...:?: :-? Any ones can point me about...
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    Differential amplifier design

    Hi serma, As far as i know, W and L of differential input pair will be consider by some following specifications: 1. W/L is large to increasing gm, so it means that gain also increases. 2. L need to be small, and W to be large to minimize device offset: Vos is ~ 1/(W*L) Normally, depend on the...
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    nmos G/S/B connected to gnd

    When you connect G/S/B of NMOS to gnd, it will act like capacitor.
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    how to simulate SNDR and SFDR of ADC with HSPICE

    Hi mohsen941, You can use ADC toolbox in tool spice explorer, it's very helpful to view SNDR and SFDR results. And then read this thread: https://www.edaboard.com/threads/148544/ Hope this help!
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    LDO design procedure help

    Hi rvidya, I have already designed LDO, and as far as i know, the tutorial: Low drop-out(LDO) linear regulators: design considerations and trends for high power supply rejection (PSR), the author is: Edgar Sanchez - TMU is very helpful. Another useful document is the book: "Analog IC Design...
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    gain of two stage op amp

    Hi daintyvlsi, To calculate the gain of this circuit, the first thing you must do is fixing your circuit as some guys mentioned above. And then, you draw the small signal equivalent circuit, you will that the gain is: Av = gm2*(r02//r04)*gm6*(r06//r07) After that you can build a test-bench...
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    Why use bandgap reference voltage 1.024V???

    Hi diarmuid! So, why 1.024V, it's for 1LSB => good for standardization of ADC. ;-) And normally, this is reference voltage, i think it should not be called bandgap ref voltage, because the typical bandgap voltage is between 1.2 - 1.3 V, it is based on the theoretical value for silicon is 1.22eV...
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    reference voltage of the bandgap reference circuit by using 0.13um CMOS silterra tech

    Hi kk913913, I designed bandgap with Vref = 0.5V using 0.18um process. I also followed the paper that palmeiras mentioned above, it gives the good circuit. And here is my circuit: Hope this helped!
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    differential amplifier

    Hi abdou8_x! Normally, PMOS-pair and NMOS-pair are the same, maybe diff.pair used a lot in error amplifier and opamp...=> it depends on the output stage of your circuit. Also, it depends on your specification design. For example: Gm, slew rate, output swing, phase margin, gain margin, DC gain...
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    designing an IC for beginner

    Hi XC.6800! I am an undergraduate student ^_^. Also, i am newbie in IC design, i focus on analog IC design. - I follow the courses about analog IC design of UC Berkeley, i can easily find them in the internet, each course includes: lecture notes, video, homeworks, test, also recommended book...
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    Bandgap Startup circuit needed , with voltage limited devices

    Hi dominoeff! I see that you are designing the startup circuit for LDO, i suggest that if your reference voltage is designing based on bandgap principle, the reference current should bias for some sub-block inside bandgap, and startup circuit you can use and array of NMOS is biased by current...

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