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  1. S

    PMOS switch bulk connection

    hi all I have a problem when I design a sampling circuit. The sampling cap is very big, so the switch (which is a CMOS switch) resistance should be very low to get a good sampling presicion. but the PMOS size is very big to get a low resistance. The bootstapped switch is not suitable...
  2. S

    comparators with 1.8V power supply

    I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure). the process i use is 0.18um, and the parameter...
  3. S

    the offset of the dynamic comparator

    offset, dynamic comparator I am designing a comparator which allows +- 50mV offset, is the architecture attached here easy to achieve the specification? the process is 0.18um, and the power supply is 1.8V. thank you in advance!
  4. S

    the proper value of Vgs-Vth of the input MOST

    I am designing a folded cascode OTA for pipelined ADC. It requires 400M Hz GBW with lowest power consumption. the load capacitance is fixed (i.e. 4 pF), so i need to design the input MOST to get the largest gm under the lowest id of the input MOST. as we know, gm is inversely propotional to...
  5. S

    simulating the settling time of "FDA with SC-CMFB"

    ota settling time I have designed a Fully Differential Amplifier (FDA) with Switched Capacitance CMFB, which is used in pipelined ADC, but I wonder how to simulate the settling time of it. It is different from the OTA with continuous time CMFB because it's working in discrete time or just one...

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