Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
FPGA is based on LUT and FF while ASIC based on gates only.
FPGA used fixed MEMORY blocks while ASIC is custom.
FPGA PLLs differs than ASIC PLL
FPGA production technology is completly deiffernt than ASIC.
So it is not possible to evaluate power of ASIC based on FPGA.
you suggerst two soluations:
1. implement all the equation by using memory only.
2. using less memory but using also 3 multipliers.
which soluation is better for ASIC and whichfor FGPA? is there any other consideration?
I have asked about implemetation of X^2.5 while X is a vector of 8-bit.
No alhorith implemetaion is required.
I have suggested the following solution:
for X^2 I will use simple multiplier(X*X).
X^0.5 I will use ROM.
then I will multiply the results.
Why do you need such this data???
what the content of this data???
You should take care about programming the FPGA with incorrect data. You may cause unexpexted result in FPGA.
Generally when programming the FPGA, the programmer should take to erase the content of the FPGA to insure that the...
Gate delay(LUT) can be calculated from the vendor datasheet. The net delay is never calculated in advanced because it depends on the place and route so it is keep unknown till you have the result of the PAR; then you will have a detailed report regarding each net/trace.
This is the way that I am using SW_RST. In addtion:
1. I sample the OR output gate to same clock domain.
2. as a global reset is synchronized; it will be traeted in the process as asynchrnous one to insure that evently reset can NOT affect FF at S/H time window.
3. limiting the...
You just have to include proc_common_pkg:
If proc_common_pkg.vhd is complied to WORK directory so:
I am using Altera'Startix-II with out NIOS.
I only using its memory and logic.
I want to build a component that holds the version of the current FPGA image.
this version is incremented every new version of FPGA so I can read it by Read Only register.
I have no flash.
In the past, when I used...
represent fractions in vhdl how
supposed an unsigned vector A_UNS which represent 4.3 in form q.r:
4 : represents 4-bit of the QUOTIENT
3 : represents 3-bit of the REMAINDER
decimal vector 9.125
is represented in binary as A_UNS="1001.001"
the simulator will show A_UNS as 73...
I have several HW implementaion blocks that I develop.
I want to share them but I don't want the other ppl to see its content.
Just to use it as black box.
something like EDIF files.
how I can generate like this desire???
synchronous process with non blocking
when I have a case statment in a synchronous process, can I leave WHEN OTHERS with no value???
In Aynchronous process I should insert values to make sure that no latch will be produced. but what about synchronous process???
What is the functionality different or the implication of next two situations:
1. An output of OR'gate that is feeding TRI_STATE buffer and that buffer is feeding a PIN output.
2. OR'gate output is connected directly to a PIN output while OR'inputs are connected to two independent TRI_STATE...