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  1. V

    How to simplify the multiplication with a binary sequence

    Fine .....you can extend the concept .......for multiplicand 1 and -1 only ....Detect from input streamif its 1 copy the multiplicand as it is....If its -1 take 2's complement of multiplicand ,Shift the partial product.....sign extend and Add partial product ....Try it for small numbers and...
  2. V

    Manipulating character matrix into array in Matlab :

    Upon converting an input array into hex using Hex_LEN_INPUT = dec2hex(LEN_INPUT).My output appears as ... out = 0e68 1b59 2927 >> whos out Name Size Bytes Class Attributes out 3x4 24 char But I need my output to be as row vector like ... out...
  3. V

    How to simplify the multiplication with a binary sequence

    For both signed number Multiplication ,You need to consider few things 1-Sign extend results of partial products 2-For sign bit multiplication (if its 1 ) take 2's complement of multiplicand. 3-Ignore the carry out from MSB to get the accurate result... 10...
  4. V

    Clearing Block ram in verilog HDL

    because of my design..... 1-I need to calculate histogram of an image.For that I need to store an image in BRAM,store calculated histogram of image in another Bram that Bram needs to be cleared before writing any data..... 2-To add more Why....I need to count the frequency of every image pixel...
  5. V

    Clearing Block ram in verilog HDL

    Yes you are right but Ineed to store an image in BRAM and it must be cleared to zero before any operation.I got ur point one write per clock cycle but in case of large BRAM it will increase resources,decrease speed considerably.....any other idea....
  6. V

    Clearing Block ram in verilog HDL

    I had made a dual port BRAM (separate port for read / write ).I want to add an input that clear the BRAM when its high.... How can I do this for 256 x 8 Bram so that my code is synthesis able and could be modeled in hardware/Technology....one approach is to use for loop but requires more...
  7. V

    Looking for UART Verilog model

    Re: uart model I tried to visit that site for Micro uart model **broken link removed** but it had been removed from there can you email the files at waqasanjum86@gmail.com with description regards,:!:
  8. V

    Verilog n-bit wide 2x1 Mux

    I had read it in books and googled it before writing it in post.Please browse it to topic 14.4 Unsupposrted constructs of this link and tell me as well. htttp://eesun.free.fr/DOC/VERILOG/verilog_manual1.html Yes your second parametrized approach is right.Thanks for it.
  9. V

    Verilog n-bit wide 2x1 Mux

    yes i knew code for mux as well as defparam too.but defparam is non-synthesizable construct so it is ruled out too.any other way of doing it..
  10. V

    Verilog n-bit wide 2x1 Mux

    Dear All, I had written verilog HDL behavioral code for 4 bit 2x1 mux but my requirement is that i want a generalized code so that i can call it from top level module based upon width of my data. I want that mux code to behave as 4-bit wide 2X1 mux or on requirement 8-bit wide 2x1 mux as well...

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