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  1. achaleus

    CDC for constant signal

    always @ (posedge clk_153) begin if (reset) start_reading <= 1'b0 ; else begin if(condition1) // once this condition occur start_reading is always high start_reading <= 1'b1 ; end end always @ (posedge clk_102) begin if (reset) read/_en <=...
  2. achaleus

    What is the exact use of Wrapping burst transactions in AXI 4 ?

    Dear EDA Board members, let us take one example with Burst Length=8, Number of Bytes=4 and Starting address=0x4a and data needs to be transferred using Wrapping Burst. I have calculated the address of each transfer with respect to equations given in AMBA AXI Protocol Version 2.0 Specification...
  3. achaleus

    Anti aliasing in VIPT cache

    Dear edaboard, While designing a cache we should satisfy the condition cache size <= BLOCK size * set associativity, if we increase cache size or by decreasing associativity we ran into aliasing problem. there are very less information available regarding overcoming aliasing (anti aliasing...
  4. achaleus

    C library call from assembly generated by gcc from some c code

    I am experimenting on modifying assembly by calling c library from assembly, I ran into segmentation fault exp1.c contains #include <stdio.h> double *a,*b,*c; int main() { double a_d = 1.1; double b_d = 2.1; double c_d; c = &c_d; a = &a_d; b = &b_d; *c = (*a + *b); printf("\n%lf",*c); }...
  5. achaleus

    -msoft-float -m64 x86 machine, gcc is not referring to software floating point librar

    Dear edaboard, I have a third party software floating point library which was compiled using 64 bit machine (-m64). I am trying to infer this floating point library using gcc flag -msoft-float. If I am using gcc -msoft-float -m32 flag for c = a+b, where c,a,b are float values,gcc infers...
  6. achaleus

    How can I monitor a signal in post synthesis .v file

    Hello everyone, I am using ISE 14.7 for synthesis and Questasim 10.0c for simulation. I am doing post synthesis simulation to find out simulation and synthesis mismatch. ISE elaborated all hierarchy files into a single file for e.g. \instance1/my_signal[15:0]. The signals generated are so vast...
  7. achaleus

    [SOLVED] timing problem in doing CLOCK DOMAIN CROSSING

    While doing CDC, I am using 3 flop synchronizer from slow clock(100MHz) to fast clock(250MHz). It is reporting timing not met as (I am using xilinx 14.7 for synthesis) Source Clock: clk_100 rising at 10.000ns Destination Clock: user_clk rising at 12.000ns but actually it should report...
  8. achaleus

    Forcing a variable in Modelsim or questasim simulation

    Hello edaboard, how can I force a variable/signal in modelsim/questasim to all ones. suppose I have a signal with vector length 512 so how can I force to all one's thank you, achaleus
  9. achaleus

    Unable to generate ap_idle as high in Vivado HLS

    Hello edaboard, I have written one module in Vivado HLS, where simulation waveforms are fine. I generated EDIF from Vivado design suite converted to .NGD using ngdbuild and to verilog using netgen tcl commands from xilinx and done simulation using modelsim. There ap_idle is not getting high...
  10. achaleus

    [SOLVED] How to synthesis files taken from Vivado hls

    Hello all, I have done Synthesis, co-simulation and after test passed I exported to rtl(Ipxact) using Vivado HLS tool. I wanted to test on board which has virtex 6 fpga. So, I tried taking all rtl files and synthesizing on ISE 14.2 tool but unsuccesful. Vivado generated so many files, I don't...
  11. achaleus

    Suggestions required where to start using DSP kits

    Hello edaboard, Currently I am working on FPGA, now my head told me to explore on DSP kits that they will provide me 2 to 3 DSP kits(I don't know which kits they are!!!!). I have to do some projects on it... I don't know where to start, what knowledge should I have to do on these...
  12. achaleus

    [SOLVED] big bang doubt, what made them decelarate

    Hello all, It was said that whole thing originates from big bang. This whole universe,galaxies,gravitational waves all came from a very very small densely packed with infinite volume particle (what so ever I don't know what it is ) exploded... my question is as there is no external force acting...
  13. achaleus

    matlab floating point doubt

    Hello all, 18446744073709551615 - 3 and 18446744073709551615 output in cmd line in matlab giving same output as 1.8447e+019. my ques is how to see exact value as 18446744073709551612
  14. achaleus

    linpack libraries on FPGA

    Hello edaboard, Currently my work is assigned to design linpack libraries on FPGA, I am implementing basic linear algebra subsystems i.e. add,sub,transpose,scalar and dense vector multiplication with real 32bit and imaginary 32 bit. I haven't given any size of the matrix...
  15. achaleus

    [SOLVED] problem regarding xilinx multiplier ip core

    Hello edaboard, after generating xilinx multiplier ip core v11.2 ( release version 14.2, applicaton version p.28xd) width 32x32 bit expecting 64 bit output in which 6 stage pipelining is selected, using mults based multiplication . I am expecting output after 6 clock cycles...
  16. achaleus

    convert audio into time domain samples in matlab

    hi all, I want to see what are the frequency components present in my audio, I will use FFT operator to convert time domain to frequency domain and I will plot to see frequencies. please suggest how to sample the audio(say no' of samples are 1024 so that I can use 1024 point fft) in matlab
  17. achaleus

    use of multiple IP cores in vertex 6 fpga

    hi all, I have an designed IP core, which was successfully tested on board(pico M503), now I am doing multiple(same IP) cores but I am facing timing problems but for single core it is worked fine, I am using smart explorer for various ways of mapping and I am checking there timing...
  18. achaleus

    generate staement problem while using case... (urgent)

    hi all, I want to generate case conditions, I wrote like this but state is not inc and output is wrong.. just help me how to write these generate statement, I need to repeat the code inside case condition (say 100) according to 'j' value and has to change state also(next case condition)...
  19. achaleus

    How to give high impedence in verilog

    hi all, Is there any way to give high impedance in verilog. I tried to give 10'bZ, bufif0,bufif1.. but it is taking all one's(I say in post synth simulation) . I am using vertex 6 fpga..
  20. achaleus

    [SOLVED] post synthesis problem in ram1024x64

    Hi edaboard, In my project I am using dual port block rams... Functional simulation is correct but for post synthesis simulation my output results are wrong.. I saw nets and reg (both input and outputs using "KEEP" attribute) input data and address lines are going correct, but...

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