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    what does bit blasted netlist mean??

    I recently came to know about gate level netlist files which are also bit blasted... now does anyone know what is the difference between normal netlist and bit blasted netlist??
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    how to pass array in mailbox??

    How can one pass array in mailbox in VERA or SV??
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    What is the difference between SAIF and EVCD file??

    what is evcd Also how is the SAIF file used in power estimation??
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    ignore lines from file while reading by fscanf in verilog

    Is there any way to ignore commented lines in file, while reading data by using fscanf function in verilog?
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    Can we use current_state/next_state signals for particular output signal generation?

    Just a concern about output signal generation from FSM... Can we use current_state and next_state signals for particular output signal generation? // cosider below FSM is based on one-hot encoding :| e.g. fsm_out = ( !cur_state[7] && next_state[7]); Is it bad coding style? If Yes, then why?
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    How to get parallel hardware in simulation using case statment?

    Till now, i was under impression that case statment will generate non-priority encoder hardware both in simulation and synthesis, but following coding shows that in simulation in works like proirity encoder... :-( module m (); wire [3:0] w1 = 4'b1101 ; initial begin #4; case(1'b1)...
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    How to read one line at a time from a file in Verilog?

    Does anyone know how to read one line at a time fron a file, in verilog? readmemh reads the whole file, but i just want to read one line at a time. Any idea?
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    How can we decrease clock skew?

    How can we decrease clock skew? i heard somtimes it is good to have in design, then why is that so, i mean how can it be helpful?
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    Negative setup and hold time

    negative setup and hold time Recently i heard about "-ve" setup and hold time. Can any one please, explain in detail with examples about it? Thanks in advance...
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    How does compilers (like VCS) read the encrypted RTL?

    How does compilers (like VCS) read the encrypted RTL?
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    verilog scheduling semantics

    In verilog scheduling "Monitor events" are the execution of system tasks $monitor and $strobe. Now as $strobe and $display are not same, which kind of event $display system task is? Is it Active, Inactive or Future event?
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    silicon design methodology

    Does any know , how many methodoloy are there for an ASIC? recently i came to know about one: https://www.open-silicon.com/Sites/opensilicon/content.cfm?id=272 If anyone knows any other than please share it.
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    How license servers are set up?

    Can anyone provide, information regarding how license servers are setup? and how license files get shared accross the network?
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    What is the use of totem-pole output?

    What is the use of totem-pole output? Somewhere it is defined as three state o/p and somewhere else as two state o/p, what is correct out of both?
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    Where can I find Verilog LRM 2001 or 2005?

    Can anyone please tell where can i find verilog LRM 2001 or 2005?
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    How to call Perl script from Verilog?

    Anyone knows how to call perl script from verilog? please reply as soon as possible. thanks in advance for the reply.
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    What is the exact design flow of any digital chip?

    What is the exact design flow of any chip? I only know abt verilog coding and than at the end something like, tape-out of chip occurs, but what comes in between, and what after the tape-out?
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    Pull up resistor in I2C communication

    Can anyone please explain the communication over i2c bus? if master releases a line after transmitting address on the SDA, the pull up resistor will pull that line to logic HIGH, now If slave drives SDA to logic LOW to provide ACK. won't this condition create "X" on SDA line?

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