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Just a concern about output signal generation from FSM...
Can we use current_state and next_state signals for particular output signal generation?
// cosider below FSM is based on one-hot encoding :|
e.g. fsm_out = ( !cur_state && next_state);
Is it bad coding style? If Yes, then why?
Till now, i was under impression that case statment will generate non-priority encoder hardware both in simulation and synthesis, but following coding shows that in simulation in works like proirity encoder... :-(
module m ();
wire [3:0] w1 = 4'b1101 ;
In verilog scheduling "Monitor events" are the execution of system tasks $monitor and $strobe.
Now as $strobe and $display are not same, which kind of event $display system task is?
Is it Active, Inactive or Future event?
Does any know , how many methodoloy are there for an ASIC?
recently i came to know about one:
If anyone knows any other than please share it.
Can anyone please explain the communication over i2c bus?
if master releases a line after transmitting address on the SDA, the pull up resistor will pull that line to logic HIGH, now If slave drives SDA to logic LOW to provide ACK.
won't this condition create "X" on SDA line?