Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You need to point it at the cadence tools library (e.g. $CDS_INST_DIR/tools/lib)as well as your own library directory(e.g. EXPORT LD_LIBRARY_PATH=$ LD_LIBRARY_PATH:/home/xxx/xx/, the directory is your local directory which contain file libudm.so)
what is wlm
WLM here stands for wireload model.
for top, it means all net use the same wireload as which used on the top level, so the wireload used on hierarchical cells has no effect. if you used the flattend design to layout, you can chose this mode;
for enclosed,it means the wire load...