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  1. B

    How can I convert Verilog code (gatelvel) to Schematic?

    converting verilog to schematic capture Hi, You can try debussy or verdi
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    What is DFM and where do we check it?

    DFM DFM stands for design for manufaction.....
  3. B

    error when run the LDV simulator

    You need to point it at the cadence tools library (e.g. $CDS_INST_DIR/tools/lib)as well as your own library directory(e.g. EXPORT LD_LIBRARY_PATH=$ LD_LIBRARY_PATH:/home/xxx/xx/, the directory is your local directory which contain file libudm.so)
  4. B

    how to convert *.ape files to mp3

    open ape files try foobar2000
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    Explanation of the WLM settings

    what is wlm WLM here stands for wireload model. for top, it means all net use the same wireload as which used on the top level, so the wireload used on hierarchical cells has no effect. if you used the flattend design to layout, you can chose this mode; for enclosed,it means the wire load...
  6. B

    Why we fix Hold after CTS?

    Hold avoid to insert too many buffers
  7. B

    Can function be used in Verilog RTL?

    Re: function used in RTL Right, Function are usually used for implementation some combination logic at RTL level
  8. B

    what's difference between USB2.0 and USB1.1 ?

    usb2.0 usb1.1 different PHY is the bigest diffrence
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    How I can exicute eda tool on windows-xp from linux server

    you can try VNC, very easy to use
  10. B

    PIC micro and stepper motor schematics

    stepper motor schematics https://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1515
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    what is "delay_mode_unit" for ncverilog?

    ncsim assign # delay mode no, delay mode is used for cell delay
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    What are the isolation cells and what is their significance in DFT?

    Isolation Cell Isolation cells is used to prevent physical damage to sections of the IC that interface to power switch-off modules in low power design.
  13. B

    ne verilog and vhdl code book

    A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog ( HDL Chip Design ) by Douglas J. Smith
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    What does R mean in ncverilog -R?

    ncverilog -R -R: The -R option lets you simulate the same snapshot multiple times using different simulator command-line options.
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    synchronous reset or asynchronous reset?

    asynchronous and synchronous reset quite right,It depends.
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    Does NC-Verilog work on Windows platform?

    nc-verilog windows download NC-verilog 5.1 has a windows platform version, but I think many EDA tools of ca#dence or synopsy#s on windows platform are not stable for use.
  17. B

    Looking for project that uses OCP-IP protocol

    OCP-IP protocol some MIPS CPU IP is designed with OCP interface

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