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Dear all, I simulated a simple inductor in HFSS and Sonnet. The inductance value is similar, however, the Q value simulated by HFSS is much smaller than that obtained by Sonnet. I am very puzzled at this, does anyone know the reason?
Hello everyone, I want to consult you that how to choose a proper kind of transistor before your design. For example, if I want to design a PA, should I choose NMOS or NMOS_rf transistor? How about the voltage? I designed IC before, but choose the same transistors which my friends used. While I...
I want to simulate the schematic of an easy circuit, but failed. I checked and found I don't add the model library, but how many files should be added and which ones? I am still puzzled. Does anyone know?
Besides, what's the meaning of 'tt' in the 'section'?
Thank you very much.
Hello everyone, when I do LVS check in cadence, I find this problem in the picture. This layout can pass the DRC check, and I am sure the devices in the layout are the same as the ones in schematic.
Does anyone know the reason? Thank you deeply!
Hello everyone! I read a paper but I am puzzled when I read this sentence.
In my mind, I think the resistance at gate is extremely large, how can it became negative after an inductive impedance is connected to the drain?
Hello everyone! I want to simulate the schematic in ADS, but the problem occurs when I change a new designkit. While, I can simulate succesfully by using another designkit.
Does someone know te reason?
Thanks a lot!