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  1. S

    What's the difference between running the DC in normal vs the topographical mode?

    Hi RCA, I appreciate the response. But doesnt dc_shell use the same wire load models, and loads the same libraries (fast, slow, tt libs for best, worst, tt cases) for the estimations? Although, I would like to know more about how these estimations are more precisely done in topo mode? I was...
  2. S

    What's the difference between running the DC in normal vs the topographical mode?

    I'm trying to learn more about the topo mode with Design Compiler. And other than few additional commands that the topo mode has, I couldnt tell the difference. Thanks for any clues on this. S
  3. S

    [SOLVED] DDC file Synopsys - what does it contain?

    Hello All, I have been trying to find what information does the DDC file contain. Thank you.
  4. S

    [SOLVED] ICC Error - Module 'NOR2X0' is not defined. (MWNL-297)

    Hey, were you able to solve the issue?? I'm facing the same problem... I used -allow_undefined_module as suggested by the error message. So, its not giving any errors now... but I don't see the FRAM being used in my top level module. Thanks. ---------- Post added at 05:38 ----------...
  5. S

    [SOLVED] Plot in LTSpice - Vt0 vs. Vgs

    Hello, Im trying to plot Vt0 vs. Vgs keeping a Vds constant. In the 'pick a visible trace' list, I can see all the currents and the circuit voltages - but not the device parameters. Please find the circuit below - its a real simple circuit. Any help is appreciated. Thanks ssti
  6. S

    SoC Encounter crashes while importing Verilog netlist

    yes. we are working in 64 mode.... any other clues?
  7. S

    SoC Encounter crashes while importing Verilog netlist

    no.... i use 8.1 and im having the same error. I also get the same error (rather warning) after it imports a LEF file. @busoni: The module for which you get the 'antenna' error - is is a hard macro by any chance?

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