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Remove the "end if" below the line "pr_data <= (others => '0'); as shown below:
READ_REGISTER_PROCESS : process(clk)
if (clk'event and clk = '1') then
if reset = '1' then
prdata <= (others => '0');
case paddr(8 downto 2) is
The use-statement given does not point necessary to a package declaration. It points only to a library hwicap_v5_00_a which maybe has only entity/architecture declarations in it.
A use statement pointing to a package declaration has the form:
Your schematic looks fine to me. I do not know the output file of promgen. I have never used it.
I am not aware of a Xilinx document with such a schematic. Even it makes sense for every designer.
You can mix VHDL and Verilog if your simulator and synthesizer supports both languages (is sometimes an add-on feature).
In your Verilog code instantiate your VHDL ip-core just like if it was a Verilog module.
Line 52: contains a generate statement. A generate statement must have a static (fixed) condition. You use a signal "stepsize" in this condition. A signal is not a static. Change the signal in a constant (static) and this error will be fixed.
The same applies for the other generate...
I have done a quick simulation with your uart code and in my simulator n_reg will be '0' after reset.
From your simulation picture I can not see how long the reset pulse is and how it behaves compared to the clock. Maybe you can post your testbench code also so I can use it with my...
architecture xxxx of yyyy is
file fin : text open read_mode is "<path to your hex file>";
variable rdline : line
variable hex : std_logic_vector(3 downto 0);
Re: VHDL: How to convert 2D std_logic array element into str
Maybe the image package (image_pb.vhd), written by Ben Cohen, has a function you can use for this. His website is systemverilog.us, select VHDL Models & Papers.
It are packages you never use when you write your own code :wink:
In my opinion, in the past they were used by Synopsys Design Compiler in the generated gate-level netlist. From the components list of DigitalLogican it is/was an ASIC package.
I guess it is hard to find...
You must tell the translate process where to find the ngc file. When you use the GUI you can do this in the process properties of "Implementation" and specify the path to the ngc file in the "Translate Properties" > "Macro Search Path".
In batch you can use the "sd" switch (-sd <path>) in...