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  1. D

    Signal prdata cannot be synthesized, bad synchronous description.

    Hi, Remove the "end if" below the line "pr_data <= (others => '0'); as shown below: READ_REGISTER_PROCESS : process(clk) begin if (clk'event and clk = '1') then if reset = '1' then prdata <= (others => '0'); else case paddr(8 downto 2) is when...
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    problem with test*bench verilog at models*im

    Hi, When compiling your code with Modelsim I get 2 errors about signal sel. Remember Verilog is case sensitive! After changing this I do not get any compile error in the part you posted above. Devas
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    Looking for library declaration of IP Module

    Hi, The use-statement given does not point necessary to a package declaration. It points only to a library hwicap_v5_00_a which maybe has only entity/architecture declarations in it. A use statement pointing to a package declaration has the form: use <library>.<package>.<suffix> Your use...
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    Xilinx synthesis and PNR flow

    Hi Beowulf, Your schematic looks fine to me. I do not know the output file of promgen. I have never used it. I am not aware of a Xilinx document with such a schematic. Even it makes sense for every designer. Devas
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    Verilog Question about Always sensitivity list

    Hi, always(*) is Verilog-2001 syntax. It simplifies the sensitivity list. * means be sensitive changes on any values which are read in the following group. Devas
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    [SOLVED] verilog and vhdl in same project, problems

    Hi, When your simulator/synthesizer has mixed language support there is no need for XHDL. Devas
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    Xilinx synthesis and PNR flow

    Hi, A starting point: - Xilinx Synthesis: XST User Guide (UG627) - Command Line Syntax/Tools: Command Line Tools User Guide (UG628) Devas
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    [SOLVED] verilog and vhdl in same project, problems

    Hi, You can mix VHDL and Verilog if your simulator and synthesizer supports both languages (is sometimes an add-on feature). In your Verilog code instantiate your VHDL ip-core just like if it was a Verilog module. Devas
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    How to start implementing transmitter and receiver on fpga using VHDL or verilog

    Hi, Open a text editor and start typing: VHDL: "library ieee; ...." Verilog: "module transmitter(...."
  10. D

    Help regarding error in ise synthesis

    Hi, Line 52: contains a generate statement. A generate statement must have a static (fixed) condition. You use a signal "stepsize" in this condition. A signal is not a static. Change the signal in a constant (static) and this error will be fixed. The same applies for the other generate...
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    [SOLVED] xilinx core generator

    Hi, CoreGenerator is part of the Xilinx ISE software. You can download it from the Xilinx website. The webpack version is free and includes also CoreGenerator. Devas
  12. D

    problem in initialization

    Hi, I have done a quick simulation with your uart code and in my simulator n_reg will be '0' after reset. From your simulation picture I can not see how long the reset pulse is and how it behaves compared to the clock. Maybe you can post your testbench code also so I can use it with my...
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    Quartus Ver 4.2 & Nios 3.2 shell - Compiling error !!!!

    Re: Quartus Ver 4.2 & Nios 3.2 shell - Compiling error ! Hi, You use a very old Quartus version. I do not believe that version is supported on Windows Vista. Devas
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    help with reading a hex file in vhdl

    Hi Haneet, Something like: library ieee; use ieee.std_logic_textio.all; library std; use std.textio.all; architecture xxxx of yyyy is file fin : text open read_mode is "<path to your hex file>"; process(zzzz) variable rdline : line variable hex : std_logic_vector(3 downto 0); begin while not...
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    help with reading a hex file in vhdl

    Hi, The package std_logic_textio has functions (HREAD) to read hex values from a file. Devas
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    VHDL: How to convert 2D std_logic array element into string?

    Re: VHDL: How to convert 2D std_logic array element into str Hi, Maybe the image package (image_pb.vhd), written by Ben Cohen, has a function you can use for this. His website is systemverilog.us, select VHDL Models & Papers. Devas
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    VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

    Re: VHDL netlist. Have a look in the file XXXXX.vhd at line 82 and check this line.
  18. D

    VHDL: lsi_10k.COMPONENTS.all; work.CONV_PACK_reg.all

    Hi TrickyDicky, It are packages you never use when you write your own code :wink: In my opinion, in the past they were used by Synopsys Design Compiler in the generated gate-level netlist. From the components list of DigitalLogican it is/was an ASIC package. I guess it is hard to find...
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    VHDL: lsi_10k.COMPONENTS.all; work.CONV_PACK_reg.all

    Hi, Try to post your question to comp.lang.vhdl. Maybe on that newsgroup is someone who can answer your question. Devas
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    Xilinx core generation error (cordic)

    Hi, You must tell the translate process where to find the ngc file. When you use the GUI you can do this in the process properties of "Implementation" and specify the path to the ngc file in the "Translate Properties" > "Macro Search Path". In batch you can use the "sd" switch (-sd <path>) in...

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