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  1. S

    Technical test round and interview at Sandisk(VLSI)

    Re: About Sandisk They came to recruit students for ASIC design....but test questions were completely related to analog.... like amplifier gain ..resistance and all....it was quite tough....
  2. S

    BLock Ram's value....

    Can we use chipscope tool or timing analyser tool available with xilinx to see internal signals of 170 bits.... how feasible would it be??
  3. S

    BLock Ram's value....

    how can we take out around 170 bits output at one stroke... shud we stop processing for time bein usin enable/disable signal and then take output thru serial/parallel port to PC or is there some other way....
  4. S

    BLock Ram's value....

    i am using virtex 4 board.... i have one complete matrix o/p stored in block ram...i want to read at certain interval of time to verify the answer.... how can "readback capture " can be performed ???? wat tool is required...
  5. S

    BLock Ram's value....

    Can anyone tell me whether is there any provision to know the values stored in block ram at every small instant of time thru serioal or parallel port without outputtin the values during testin input after synthesis in FPGA....
  6. S

    Technical test round and interview at Sandisk(VLSI)

    Can anyone give me the idea about technical test round of sandisk(VLSI) and about interview...like about what will they ask...please
  7. S

    any one answer to this questions

    Frequency Modulation --- Granular Noise
  8. S

    What wil happen if the power supply in the CMOS inverter are interchanged?

    What wil happen if the power supply in the CMOS inverter are interchanged....i.e.,if Vdd is connected to source of NMOS and GND to PMOS source..... I feel it will work at subthreshold region only....What is your views....
  9. S

    Help...C code for parallel port communication ...

    Oh thanks....so can we send data parallely..? How to enter bitstreanm in it and send it??
  10. S

    Help...C code for parallel port communication ...

    Can anyone provide me C(or C++) code for parallel/serial I/O port connection with Xilinx board using communications port(COM1/COM2) port of my computer... or can anyone provide me with the pdf for communications port in PC which gives details of address of each reg/port inside....
  11. S

    Advantages of latch over flip flop

    Time sharing and time borrowing is the significant adv for latch in case of robust design.....But still latches are not prefferd over FF.... Using JK FF we can implement many function with lesser number of combinational gates...thus lesser delay....whereas with D FF size of Comb block will...
  12. S

    BER for M array orthogonal signal

    Thanks Darock, But u see in M-QAM ...LSB bits are coded with ASK and MSB bits are coded with PSK...so there is lot of diff....as we know that PSK has min probability error....
  13. S

    Solvin differential equation.....

    close all; clear all; vact=0.8427e-16; %active volume of laser cavity gco=8.0e-11; %gain constant Nctr=0.59e23; %transparency electron density tn=3e-9; %spontaneous recombination lifetime tp=0.7e-12; %photon...
  14. S

    Hey Guys One Interview Question! Beat the hell out of Me!!

    Re: Hey Guys One Interview Question! Beat the hell out of Me It could be some kind of comparator....
  15. S

    Buffer & Clock buffer??

    clock buffer requires very high FAN OUT....and lesser delay as possible....so it is design exclusively and those are huge in size....
  16. S

    BER for M array orthogonal signal

    How will u prove that BER for msb bit is less than BER for lsb bits in mqam....
  17. S

    very basic question on sampling frequency..need help

    I am not normalizing freq...only power ....so freq wil run from 0 to fs/2.....power need to be normalized....in FFT we write 1/N(...)....but in matlab when fft taken it gives it real integer values ....
  18. S

    What is the delay of a xor gate ?

    Re: stupid question ?!! U can find XOR gate delay by connecting them as a ring inverter with one input of all XOR gate at logic '1'....and other input connected to output of previous gate and so on....better to have 13 or 15 gates to get accurate time (all odd number).... Γp=time_period of...
  19. S

    The physical significant of fermi level

    Re: fermi level Hey friends i think physical significance is different from theorical explanation....please dont fill your answers with theory found in books....If anyone has imagine fermi level please let us know......
  20. S

    very basic question on sampling frequency..need help

    p is the power...tryn to plot power spectral density i suppose... p= abs(Y)/(fs/2) % Why we divide here with ( fs/2), what this tells ?? This statement means u r findin normalised power ...why (fs/2) because in fft we get the replica of positive freq on negative side....so neglectin either...

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