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I'm currently looking for a job in the analog and/or mixed-signal IC design right now. I was assigned mainly to the digital core when I was working on the SAR ADC. I do put it on my resume but most of the people questions me on the analog core. So can people throw out some potential questions? I...
I was running simulation over a boost generator but I didn't fully understand how it worked. As I understand I can look up the topic of level shifter, charge pump and voltage doubler. Please advise any textbook or slides I can find useful info.
I have a few questions about ON resistance.
1) "MOSFET can serve as a switch; it can be on when it carries zero current." This statement somehow doesn't make sense to me. Ron is the equivalent resistance across D and S so if I_DS is zero, doesn't it mean infinite resistance, or an open...
A question regarding the frequency compensation for a 2-stage OTA.
In Razavi's textbook, he assumed the dominant pole & the 1st non-dominant pole before compensation are the O/P pole of the 1st stage & the 2nd stage, respectively. He explained that to acquire each pole's location...
I have an entry-level job interview coming up soon. One of the subjects they will ask me is on bandgap reference. I do not have any design experience but book knowledge. I wonder how they would ask questions about it. So can anybody throw out some threads?
i'm given a spec and i have to achieve the gain, in TSMC018. after giving current and allocating the overdrive voltage, i did the simulation. i extracted gm and ro for each transistor, and plug the numbers into the gain equation to calculate the gain. however, the order of the magnitude of...
i've seen this block diagram for pipelined adc in many places but i'm really confused. please help me to understand this. we know this will be implemented by S/H capacitor circuit.
1)we see a 2X here. i guess this is because of capacitor charging transferring from sample phase to holding...
We're working on a pipeline ADC design and we need some help here. Our question is on the spec of the op. We're asked to get settling correct within 1/4 LSB when we input a sine wave of frequency Fs/2 of full-scale amplitude.
1) we did ask our professor what that means but we didn't really...
i have a question regarding using current mirrors to process signals. this is something razavi mentioned in his textbook. given a reference mos ckt with ideal current source Iref and (W/L)ref. the other mos ckt mirroring current from reference ckt is Ix and (W/L)x. so razavi says that if...
I'll be graduating in May. I just switched to analog design field a year now. I've designed an OPamp and done a project about noise analysis for sense amplifier. I know it's hard to find an entry-level job especially in this area. But I'll do my best.
I've noticed that many companies...
I have some questions about noise calculation.
1) we know if a transistor or a resistor is tied with a capacitor, the total noise power is kT/C. my question is, could the C be an intrinsic capacitor of a transistor?
2) the following question is for a on-going project. i really need some...
I'm trying to figure out the input referred noise power for "Sense Amplifier".
As we know that, we usually model the noise within a system as a noise source followed by a noiseless amplifer A. If the output noise power is Pop, then the input referred noise power is Pop/(A^2).
I'm working on a project. I have to run noise analysis simulation - figure out the output noise power- of a sense amplifier in cadence. But I really have no ideas how I should simulate it. It seems like, in digital circuit world, we only talk about noise margin but my supervisor wants me to...
I have a question about sense amplifier simulation. I want to know how much gain I get from my sense amplifer. I did AC analysis for an Op design before and I applied the same way I did with the Op to my sense amplifer. In other words, I set Vcm+small signal, Vcm-small signal and then look...
I have some quick questions about noise analysis for the schematic I attach.
1) I need to find the analytical solution for this circuit. I use the minimum length for all of them (I'm using tsmc018). So, when I do the calculation, do I need to use "short-channel" noise model? What we learn...
I've been reading Razavi's textbook about switched capacitor amplifier. Somehow I have a lot of questions. I don't think he explains clearly in this section. Can anyone give me a better material?
I have a fundamental question about biasing. I'm sizing the fets on cascode. I know I'm supposed to do current biasing but I still have some questions....
Suppose MN is an NMOS at the bottom of a cascode and Mb is its biasing current mirror, which is a diode-connected transistor. MN_G is...
I'm designing an op amp. Here's the spec.
GBW = 1G
power: <20mw, vin_cm =0.9v, input swing: 0.5v p-p, output swing: 1v p-p
I used folded cascode as my 1st stage and CS as the 2nd.
Overall AC response without loading cap
DC gain: 48.7dB