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  1. T

    One question about the guardring for latch up prevention

    One chip has three segments: 1) I/O pad ring (including one supply pin = VEXT, let's say 3V) 2) Core circuit (in VDD domain, let's say 1.8V) 3) One internal regulator (which generates VDD from VEXT). If putting two guardrings between the "I/O pad ring" and the "Core circuit", in order to...
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    difficult fundamental question: about delta sigma modulator

    Hi, All, I have another difficult fundamental question for the first order delta sigma modulator. ........................................................ff ........................................................| x -----(+) ----- {z^-1/(1-z^-1)} ------(+) ------> [8-bit ADC] ------> y...
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    Did anybody attend the following training course?

    Advanced CMOS IC Design '09 PRACTICAL ASPECTS IN MIXED-MODE ICs https://www.mead.ch/courses-ch/practical-aspects_ch_2009.htm
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    Challenging question for level translator

    Challenging question for level translator I have progmmable clock source Si570 (2.5V/3.3V CMOS output or LVDS output). However, I want to use it for one circuit with 1V supply (CMOS input). How to do the level shifting? Thanks. Added after 1 minutes: Notes: the jitter and clock duty...
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    Three questions about PADS 2007

    Hi, All, Two questions about PADS2007: 1) How to use fill pattern for the top metal? Please refer to the attached pic. Should I do it in "copper pour" or "plane area"? 2) For the layer type, what is the difference between CAE layer or mixed/split? 3) After the layout is done, I find the...
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    High speed, fast settling buffer

    Hi, Can anybody recommend a high speed operational amplifier circuit for the attached cicuit? Initial voltagge = 0V Settled voltage = 1V The error is about 50uV from the final value. The settling time is: 2ns Thanks a lot.
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    Ground connection in Mixed signal IC design

    mixed-signal guard ring Hi, How to connect the substrate in the following drawing? (A,B,C,D) Thanks. Tony
  8. T

    The best way to simulate full-diff opamp with sc-cmfb?

    Does anybody know how to do the AC simulation for fully-differential OTA with sc-cmfb? This is what I have heard: 1) use vcvs to model the sc-cmfb; however, what should I put the gain for the vcvs? A very large value? Please look at the attachment for the schematic. 2) Use the pac (in...
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    [Survey] What is next for mixed signal MCU?

    mixed signal mcu Currently, a lot of mixed signal MCUs are available from the market. These kinds of MCU usually contains: 1) high speed MCU core; 2) Bandgap reference; 3) ADC, DAC, Comparator & Touchsense, Comparator; 4) Oscillator; 5) POR & VDD monitor; 6) RAM & Flash; 7) Connectivity...
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    [Help] Power supply for high precision ADC test

    Hi, I am doing a high precision ADC testing (15bit). The power supply is used to power up the DUT, also to generate the reference voltage. Which option is better? 1) Use power supply's output directly, i.e., HP E3631A; 2) Use power supply's output to drive the one regulator, then the...
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    Bond bare die directly on PCB

    bare die Hi, Does anybody have the experience to bond the bare die on PCB directly? I bonded a die (delta sigma ADC) on PCB directly, without putting "conductive adhesive" between the die's backside contact and the PCB's ground. Currently, the noise level is too high (about 20dB DR lost)...
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    Can anybody check this issue for icfb?

    The procedure : 1) open a empty schematic, insert one instance: analogLib-> vpulse, fill in all the parameters as following: V3 (net5 net6) vsource type=pulse val0=0.0 val1=1 period=10u delay=1u \ rise=1n fall=1n width=5u 2) Open the ADE, use...
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    Can anybody recommend books for fully diff opamp simulation?

    Can anybody recommend books or paper for Fully differential opamp simulation? The P.Allen book is good for single-ended opamp simulation. However, the differential one is missing. Thanks.
  14. T

    Challenge question: How to simulate the input offset & n

    How to simulate the input offset & noise for the latched comparator? Thanks.
  15. T

    Spectre Simulation Switched cap circuit

    simulation switsched cap Does anybody know how to do ac analysis for switch cap circuit? Thanks. For example, the simplest switched circuit used to simulate R. How to use spectre's ac analysis to do some checking? In my circuit, one switched cap circuit is used in the gain booster amplifier...
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    In Spectre, how to simulation slew rate and noise

    slewrate spectre In Spectre, how to simulation slew rate and noise, for fully differential OTA? 1) For the slew rate, we can use unit gain buffer configuration to simulate the slew rate and settling time. How to do it for the differential one? 2) For the noise analysis, because, we have two...
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    Help me: Captab in Spectre DC simulation

    captab spectre Hi, Currently, I am using spectre to simulate one inverter, contain one PMOS and one NMOS. The input and out is labeled as "in" and "out". I just run the DC analysis with "OP" enabled. I also enable the captab. I get the following result: ******************************...
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    Is there anybody using MCU from Silicon Laboratories??

    How is it??? It seems good performace?
  19. T

    PADS Lib for PCI and PCI express

    pci express pads Hi, Anyone have the PADS library for PCI and PCI Express?? Can you email one copy to tony_taoyh@yahoo.com.sg? Thanks.
  20. T

    In RF circuit design, which ground method is better?

    Hi, In RF circuit design, using microstrip, which gound methos is better? (1) Use Via to ground; (layer 2 is ground layer) (2) Use 1/4 of wavelength (open stub). Please give a short explaination. Thanks.

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