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  1. F

    need help on VHDL 16 bit counter

    Is my testbench ok now? i need help on writing a code that can monitor the output(count) making sure it increase by 1 and able to show an error message where the error is. Should be assert statement but i don't know how to write it. library IEEE; use IEEE.std.std_logic_1164.all; entity...
  2. F

    need help on VHDL 16 bit counter

    Done my code is working already i need a code that can monitor the output(count) making sure it increase by 1 and able to show an error message where the error is. Should be assert statement.
  3. F

    need help on VHDL 16 bit counter

    Need help on 16 bit counter, how do i write statement to check on my output count making sure it count from 0 to 15 and show error message. library IEEE; use IEEE.std.std_logic_1164.all; entity counter_testbench is end counter_testbench; architecture counter_testbench of counter_testbench is...

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