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  1. M

    Problem with CRC in VHDL Ethernet MAC design

    Re: Ethernet MAC Could you please send me a link for that book. I searched the Edaboard ebook place. But there was only a solution manual. I guess you are not talking about that. Thanks! Mudu...
  2. M

    Looking for USB 2.0 Host IP Core

    Hi, Please send me a link to find a 'USB 2.0 Host IP Core'. I checked the Opencores.org, but there is only a 'USB 2.0 Device IP Core'. Thanks, Mudu...
  3. M

    Problem with CRC in VHDL Ethernet MAC design

    Hi, I'm designing a Ethernet MAC with VHDL. The problem I have is with respect to the CRC at the end of Ethernet frame. I want to know from where I have to start calculating the CRC. From books it says from the data given from the upper layer (layer 3) in ISO hierarchy. According to that the...
  4. M

    VHDL Subtype declaration

    vhdl subtype Hi, Got the point! Thanks !!!
  5. M

    VHDL Subtype declaration

    subtype declaration vhdl I declared a array as follows type matrix is array (0 to 21) of std_logic_vector(31 downto 0); I want to make a subtype out of this which has indexes from 0 to 12. Could anyone give me the coding.
  6. M

    Xilinx Spartan 3 - DCM

    Hi, Thanks! I could make the VHDL coding for that. But the simulation didn't give me expected results. Does simulation work fine, with the generated module? Best regards, Mudu
  7. M

    Xilinx Spartan 3 - DCM

    dcm in spartan I want to increase the clock twice using DCM. Could anyone exactly tell me the procedure. Thanks. Best regards, Mudugamuwa

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