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  1. T

    One question about the guardring for latch up prevention

    One chip has three segments: 1) I/O pad ring (including one supply pin = VEXT, let's say 3V) 2) Core circuit (in VDD domain, let's say 1.8V) 3) One internal regulator (which generates VDD from VEXT). If putting two guardrings between the "I/O pad ring" and the "Core circuit", in order to...
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    sdf back annotation problem with ncverilog. PT spef sdf

    I have same problem as described, with following setup: a) PT: 2012.12 b) NC: ius10-20.021 #1. I tried "set_host_options -max_cores 1", it does not work. #2. After trying about 3 hours, I found the solution: write_sdf -version 3.0 -include [list RECREM] -exclude [list no_condelse] -context...
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    difficult fundamental question: about delta sigma modulator

    Hi, All, I have another difficult fundamental question for the first order delta sigma modulator. ........................................................ff ........................................................| x -----(+) ----- {z^-1/(1-z^-1)} ------(+) ------> [8-bit ADC] ------> y...
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    low power comparator design for SAR ADC

    Hi, Pixel, Can you explain why "offset is usually not constant"? What is the assumption? Thanks.
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    glitch in the output of digital logic

    For the digital logic, you can not assume they are travelling at same speed: process variation, state dependent delay, and so on. To remove those gritches, you may: 1) Change the method to generate the input signals. For example, some gray coded counter may help. 2) You may add one latch after...
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    Did anybody attend the following training course?

    Advanced CMOS IC Design '09 PRACTICAL ASPECTS IN MIXED-MODE ICs https://www.mead.ch/courses-ch/practical-aspects_ch_2009.htm
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    Challenging question for level translator

    Challenging question for level translator I have progmmable clock source Si570 (2.5V/3.3V CMOS output or LVDS output). However, I want to use it for one circuit with 1V supply (CMOS input). How to do the level shifting? Thanks. Added after 1 minutes: Notes: the jitter and clock duty...
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    Three questions about PADS 2007

    Hi, All, Two questions about PADS2007: 1) How to use fill pattern for the top metal? Please refer to the attached pic. Should I do it in "copper pour" or "plane area"? 2) For the layer type, what is the difference between CAE layer or mixed/split? 3) After the layout is done, I find the...
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    High speed, fast settling buffer

    Hi, FvM, Thanks. Is it possible to use LDO for this situation?
  10. T

    High speed, fast settling buffer

    Hi, Can anybody recommend a high speed operational amplifier circuit for the attached cicuit? Initial voltagge = 0V Settled voltage = 1V The error is about 50uV from the final value. The settling time is: 2ns Thanks a lot.
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    Need Help: Design of 14 bits SC Sigma Delta ADC

    The simulation skill apply to any circuit: You can use transient simulation to catch some non-linear problem: for example, the output swing of the OTA, the non-linearity of the ON-resistance. However, be careful on the result: Because, device mismatching is not included for the transient...
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    Need Help: Design of 14 bits SC Sigma Delta ADC

    I think, you need to check the setting of the ideal OTA: the main thing is gain, gm, and slew rate. The third hamonica is due to the non-linearity. Normally, it is caused by the gain non-linearity and switch's on-resistance non-linearity. Hope this information helps.
  13. T

    Ground connection in Mixed signal IC design

    Are you mean to short the digital ground with its bulk connection, also the pad ring? Thanks.
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    Ground connection in Mixed signal IC design

    mixed-signal guard ring Hi, How to connect the substrate in the following drawing? (A,B,C,D) Thanks. Tony
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    The best way to simulate full-diff opamp with sc-cmfb?

    Does anybody know how to do the AC simulation for fully-differential OTA with sc-cmfb? This is what I have heard: 1) use vcvs to model the sc-cmfb; however, what should I put the gain for the vcvs? A very large value? Please look at the attachment for the schematic. 2) Use the pac (in...
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    Switch designing in CMFB of an opamp..

    For the C2 & c3, I think they are too small. Do not forget the clock feedthrough & charge injext are related to this capacitor. Try to increase them to about 50fF.
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    [Survey] What is next for mixed signal MCU?

    mixed signal mcu Currently, a lot of mixed signal MCUs are available from the market. These kinds of MCU usually contains: 1) high speed MCU core; 2) Bandgap reference; 3) ADC, DAC, Comparator & Touchsense, Comparator; 4) Oscillator; 5) POR & VDD monitor; 6) RAM & Flash; 7) Connectivity...
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    [Help] Power supply for high precision ADC test

    Hi, I am doing a high precision ADC testing (15bit). The power supply is used to power up the DUT, also to generate the reference voltage. Which option is better? 1) Use power supply's output directly, i.e., HP E3631A; 2) Use power supply's output to drive the one regulator, then the...
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    Bond bare die directly on PCB

    bare die Hi, Does anybody have the experience to bond the bare die on PCB directly? I bonded a die (delta sigma ADC) on PCB directly, without putting "conductive adhesive" between the die's backside contact and the PCB's ground. Currently, the noise level is too high (about 20dB DR lost)...

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