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Does anybody know about the internal protocol of ABB RTU560? In one of its documents, it says the internal communication of the RTU is based on IEC-101. But, when I get some data from the serial port (TL3695) of one of the cards, it does not look like 101.
I have an oscillator/counter (74HC4060) which is part of a 100%-properly-working board. The oscillator with the external resistors and capacitors, generates a 73.5 kHz pulse (pin # 9, which is CTC). I'm trying to copy this oscillator in another board and I'm using the exact R & C values...
I'm working with 80c32 micro and I have a AM29F010 Flash and a HM6264 SRAM. I have this problem that when I turn on the circuit, the SRAM WR pin which comes from micro WR pin, is not enabled at all.
What is the problem?
I'm running post layout simulation with cadence and I'm getting this error:
ERROR (SFE-23): "input.scs" 63: re1 is an instance of an unidentified model M2.
I tried in two ways: First, I ran QRC for R and C and, second I ran just for C. The first time I got this error but the second time no...
When they say, for example, a 125 MSps ADC with 2.2 GHz analog bandwidth:
1- This is called undersampling (or sometimes IF sampling), right?
2- What should the speed (the maximum clock frequency) of the input S/H be?
Designing an Opamp with 4 GHz BW
I'm designing an opamp and need 78 dB gain and 4 GHz BW with 3.5 pF Cload and 2.5 V supply voltage. I can get the gain with a single stage folded-cascode opamp, but the best result for the BW is just 1.8 GHz. Would you please let me know your opinion about this...
Suppose we have a time interleaved system (e.g. ADC) with two channels, which means the input samples are used by each channel every other one. What would the total noise of the system be? Is it going to be the sum of the noises of the channels or not?
The same question arises in double sampling...
I'm designing a 2nd order delta sigma ADC. I want to compare the systematic results with circuit design. In Matlab I have a 73 dB SNDR but in HSpice (all blocks are ideal) I have 66 dB SNDR. I don't know why? What could be the reason?
I want to use my circuit (a digital circuit) which is designed in xilinx software, in hspice. In fact I want to simulate a mixed signal system. How should I do that? Can Xilinx give me a netlist?
a question about hspice
I want to plot the drain current of a mosfet (m1) which is in a subcircuit. I use this:
.print tran i(xopamp1.m1)
in which xopamp1 is the subcircuit. The current is printed in the listing file but not in the avanwave. I use the same syntax for the current of a capacitor...
I have designed a 2nd order delta sigma modulator. In TT 25 corner the SNR is 63.8 dB. The worst result is obtained in the SF 85 which has 33 dB SNR. I want to improve the modulator performance so that it reaches a minimum SNR of 62 dB in all corners.
Is it possible to do this by improving the...
opamp output swing
When measuring the output voltage swing of an opamp, we should use a closed loop configuration. Measuring the opamp swing in open loop configuration does not make sense.
Is that right?
What is the best closed loop configuration to test the output voltage swing especially a...
When simulating a circuit that has several transistors in Hspice, we do not determine the model (one of the models that is defined in the library, for example nch.1 to nch.12) used for each of the transistors. When we run the simulation the software itself considers a model for each...
In an opamp, I want to increase the bandwidth without increasing the current. I think I should increase the gm of the output transistors whose drain constitutes the high impedance node of the circuit and the dominant pole. I do so but the bandwidth does not increase. What is wrong with the...
When I want to perform the pole zero analysis in Hspice, this warning appears:
**warning** pole analysis stopped - iterno .gt. 100
And only two of the poles are shown. The same story occurs for zero analysis.
The circuit is a fully differential opamp. When I remove the CMFB circuit the...
To my knowledge, an opamp slews if its differential input is large enough to turn off one of the two input transistor pairs. In this case the output current is limited and the output capacitor is charged with a constant current so that the output voltage will be
vo(t) = SR×t
So if the...
I wonder why we usually use three bins for the signal power when calculating FFT in delta sigma modulators? There should be just one frequency component that is the signal itself; But we use the signal frequency component, it's previous FFT component and it's next one. Why?