Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Do we need Power-Aware Signal Integrity Analysis in SerDes ?
I know in parallel high-speed digital interfaces like DDR4 we do power-aware SI analysis but do we need Power-Aware Signal Integrity Analysis in SerDes interfaces also like in PCIe.
Power-Aware signal integrity analysis of DDR4...