Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. M

    DC Optimize Registers message

    Hi, Im getting used to using "optimize_registers" in dc for retiming, everything that I'm doing seems to be working. However, I do get this output message during the optimization: Warning: The output port 'CTL_SP[28]' has output rise and fall delay that is smaller than the estimated...
  2. M

    Design Compiler Register Retiming and CDC

    Re: Design Compiler Register Retiming and Synchronization Thanks. Seems obvious now that I think about it, worked.
  3. M

    Design Compiler Register Retiming and CDC

    Design Compiler Register Retiming and Synchronization Hi, I'm using the following command to retime a design in DC: optimize_registers -sync_transform decompose -async_transform decompose I now need to change my design in such a way that adds synchronizers for 2 inputs. How can I tell DC not...
  4. M

    Synchronous Reset and Load STA and SR feedback

    Attached below is a simplified schematic showing the circuit and feedback. Also shown is a simplified diagram of how and why Im sending the reset through a synchronizer even though the DFF's are synchronous reset. The "load" signal loads "load_val" into the shift register via a selector mux and...
  5. M

    When can we avoid using reset synchronizer?

    How else can you guarantee that just after power-up the registers are in a known state? I guess if you use some pull-ups/downs you can do it but thats probably not the best design practice.
  6. M

    Synchronous Reset and Load STA and SR feedback

    I have synthesized a shift-register with feedback and adjustable feedback taps. I have two questions: 1) The SR has a load and a reset, both synchronous. Both load and reset signals come from off-chip and are not synchronous to the clk so I have sent them both through FIFO synchronizers. My...
  7. M

    Implication of not specifying input delay constraint

    Its not by much, ~20ps, I guess Im splitting hairs but yes, its better for the smaller designs. The wireload model is the standard model that comes with the PDK, in this case, TSMC65. What I meant by "more accurate" is that the P+R tool takes into account wire length. Im not too worried...
  8. M

    clock tree sysnthesis

    Re: clocktree sysnthesis Hey pal, encounter will even create the clock tree synthesis file for you, just click around.....
  9. M

    Implication of not specifying input delay constraint

    OK, let me address #1: The test setup consists of an FPGA that is sending the data to the ASIC's internal shift register. I can constrain the FPGA to output the data on the rising clock edge. The in2reg setup and hold time slacks are 1ns and 750ps respectively so I really doubt there will be a...
  10. M

    Implication of not specifying input delay constraint

    Yea, thanks. Got it. I rechecked all my timing reports and it looks like delay=0 is the default, but reassurance would be good.
  11. M

    Implication of not specifying input delay constraint

    Ok, maybe I didn't explain it right. FPGA -> ASIC (with shift register inside) The FPGA will output the serial data aligned to the rising clock edge. The ASIC, which I gave the timing constraints for in the original post, will shift in the data and then latch out a parallel stream. The ASIC...
  12. M

    DRC Violations in Encounter

    How are you checking the DRC errors? You can output a list that shows what kinds of DRC violations. Do that and post it here. Its under "verify geometry".
  13. M

    Implication of not specifying input delay constraint

    I have a serial-to-parallel converter based on a shift register and a bank of flip-flops that latches the data out. My timing constraint file is below. Clk is the serial clock and p_clk controls the output dffs. set_wire_load_model -name "TSMC8K_Lowk_Aggresive" set_wire_load_mode top...
  14. M

    [moved] Shift Register and Serial-In Parallel Out converter

    Im taping out a chip that requires a robust serial-to-parallel converter. What is posted below seems to synthesize correctly but I have the following questions: I use asynchronous resets because there are two clocks, p_clk and clk. clk shifts in the serial data, p_clk latches it out. Async...
  15. M

    Vector Modulator vs VGA+Phase shifter

    Are there any major tradeoffs between using a vector modulator or a VGA+phase shifter in a phased array? I'm thinking frequency of operation, ie, I haven't seen many VGA architectures for >5 GHz. Otherwise, there is no major difference other than the circuits themselves, you either change phase...

Part and Inventory Search