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How come a standard cell from AMS 0.35um toolkit - vert10 significantly violates design rules, e.g. NTUB to NDIFF should be 1.2um min and it is only 0.55um? NTUB enclosure by PDIF is even worse - 0.45um instead of required 1.2um.
Is there something special about those parasitic BJTs I don't know?
Is anyone aware of a complete detailed description of the older commercial CMOS manufacturing processes, something between 1um to 2um node?
There a lot of simplified process flows out there, and each of them appears to skip different steps. So I could not find an exact answer on some of the...