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  1. M

    DC Optimize Registers message

    Hi, Im getting used to using "optimize_registers" in dc for retiming, everything that I'm doing seems to be working. However, I do get this output message during the optimization: Warning: The output port 'CTL_SP[28]' has output rise and fall delay that is smaller than the estimated...
  2. M

    Design Compiler Register Retiming and CDC

    Design Compiler Register Retiming and Synchronization Hi, I'm using the following command to retime a design in DC: optimize_registers -sync_transform decompose -async_transform decompose I now need to change my design in such a way that adds synchronizers for 2 inputs. How can I tell DC not...
  3. M

    Synchronous Reset and Load STA and SR feedback

    I have synthesized a shift-register with feedback and adjustable feedback taps. I have two questions: 1) The SR has a load and a reset, both synchronous. Both load and reset signals come from off-chip and are not synchronous to the clk so I have sent them both through FIFO synchronizers. My...
  4. M

    Implication of not specifying input delay constraint

    I have a serial-to-parallel converter based on a shift register and a bank of flip-flops that latches the data out. My timing constraint file is below. Clk is the serial clock and p_clk controls the output dffs. set_wire_load_model -name "TSMC8K_Lowk_Aggresive" set_wire_load_mode top...
  5. M

    [moved] Shift Register and Serial-In Parallel Out converter

    Im taping out a chip that requires a robust serial-to-parallel converter. What is posted below seems to synthesize correctly but I have the following questions: I use asynchronous resets because there are two clocks, p_clk and clk. clk shifts in the serial data, p_clk latches it out. Async...
  6. M

    Vector Modulator vs VGA+Phase shifter

    Are there any major tradeoffs between using a vector modulator or a VGA+phase shifter in a phased array? I'm thinking frequency of operation, ie, I haven't seen many VGA architectures for >5 GHz. Otherwise, there is no major difference other than the circuits themselves, you either change phase...

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