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  1. A

    Test problem of DAC concerning the ramp data

    Hi, I've tested the DAC I designed using the ATE. But I'm confused the results. The ramp data on nth code is always different in every ramp period. For example in 12bit DAC, the output from input digital code 0100 0000 0000 in the 1st ramp, 2nd ramp, 3rd ramp .... are totally different. It...
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    problem to integraed the bridge diode

    Hi, I'm woriking on some project to design a power IC with the bridge diodes to rectify the input of 40V p-p AC to DC. I'm wondering what is the considering issue to integrate in the HV CMOS process. Please share with your experience if you had. Thanks in advance.
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    Difference between HV CMOS and BCDMOS

    high voltage cmos vs. bcdmos Hi, I'm working on the project for the class-d amp. Actually the supply needs about 30~40 due to the output power. So I'm looking for the proper process, but I'm so confused between the HV CMOS and BCDMOS process for what is cons and pros. Anyone who have exprience...
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    I need the lecture note for analog IC cource in AMSC

    Hi, Does anyone who has the lecture note for analog IC cource in AMSC? Thanks in advance.
  5. A

    What is the feedthrough current control ?

    While reading a paper, I saw the concept called "feedthrough current control" in the data communication. I'm wondering what it means. Thanks in advance.
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    Current source transistor size for DAC

    Hi, I calculated the size of the current source for the DAC, but the size came out to long channel and narrow wide, about 3/20 I think the transistor could be operated in the weak inversion region with that size. Is there any problem on that? Thanks,
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    DNL/INL test input files

    Does anyone who has the sample input files for testing the INL and DNL of D/A converter with SPICE? Thanks,
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    How to simulate the DNL and INL with SPICE

    Does anyone who has the sample input files for testing the INL and DNL of D/A converter with SPICE? Thanks,
  9. A

    how to simulate the overdrive voltage?

    Hi all, I make the overdrive voltage of transistor to 0.1V when the current flows about 1uA. So I should decide the typical size from the simulation. But I don't know how to simulate. Do I have to simulate just with diode- connected transistor with current source? Could you show me the...
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    What is the problem with the design of the bandgap with nA?

    Hi all, I'm trying to design the bandgap circuit. but it is used for the low power application, so it is allowed to consume only the hundreds of nano amphere. I'm not sure what the problem and difficulties in that case. Could you share your exprience with me? Thanks,
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    Is there specific process for wideband high performance amp?

    Hi, I'm wondering there is specific process for wideband and high performance op-amp like 2.2g GBW, 2KV/us and over 100db etc. I guess it might be BJT not CMOS. Am I right? Thanks
  12. A

    What is PROS/CONS for integrating the op-amp external?

    Hi, I've just got the new project, which is integrated the op-amp outside into inside the DAC IC. I'm just wondering there is fair reason for using the op-amp out of the DAC such as noise. Generally, what is limitation for the design of the OP-amp stand alone or integrated into a chip? Some...
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    how to reduce the gain of the VCO

    Hi all, I want to reduce the gain of the VCO to make phase noise improve. Power is 1.8V, center freq is about 500MHz and this is not a freq synthesizer so that there is no need for wide range of freqency tuning range. I use the differential amp with symmertric load as a delay cell and design...
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    Need the paper about VCO

    Hi all, I need any papers about VCO having a nominal frequency of 500MHz. It is used for the PLL block and it just will be used as a clock, so I guess it would be fine to get a low vco gain for the low jitter. I have looked at many papers, but almost are for the frequency synthesizer so...
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    Any papers about VCO around 500MHz

    Hi all, I need any papers about VCO having a nominal frequency of 500MHz. It is used for the PLL block and it just will be used as a clock, so I guess it would be fine to get a low vco gain for the low jitter. I have looked at many papers, but almost are for the frequency synthesizer so it has...
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    phase -180 -> +180 suddenly, why?

    ads phase180 Hi all, Running the AC simulation to check the stability. I have a question. The phase line is changed abruptly from -180 to +180 at certain frequency. Is that real situation or just calculation bug? I don't know how to avoid it. Thanks in advance.
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    Macro model spice simulation for current mode DC/DC converte

    dc dc converter macro Does anyone who knows about macro model spice simulation for currrent mode DC/DC converter? Any paper, documents or book would be appceciated. Thanks,
  18. A

    Regarding the input sensitivity of the USB RX

    Hi all, I am looking at the USB 1.1 Spec, but I can't understand the input sensitivity of 200mv between D+ and D-. Does it mean that the data transition should be occured within 200mv of differencial voltage or when exceeding 200mV? Also, I don't know exactly about the common mode range. I just...
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    Anyone knows the .meas for measuring the PLL jitter

    Hi all, I was told that the PLL jitter can be measured from the trasient simulation result using the .meas statement. But I don't know how to make it. Does anyone give me the example for it? Thanks in advance.
  20. A

    A Way to simulate the PLL jitter with HSPICE

    Hi all, I'm wondering how I can simulate the PLL jitter with HSPICE. I've just thought the FTT thing, but it might be a good way. If anyone who knows the way, please tell me. Thanks in advance.

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