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I guess the question really is "why derivative superposition (DS) does not help P1dB?"
DS is used to cancel out the 2nd derivative of transconductance, and the P1dB is also caused by this 2nd derivative (generally). So it should help both the IP3 and P1dB, shouldn't it?
I think not every process provides poly-poly capscitors. Is it that your target process do not have the poly-poly capacitor devices?
Do u have the PDK of the process you mentioned? Using the P-cells in the PDK will always be the preferred choice.
Hope this helps.
PS: I do have the...
Re: hspice vs spectre
I think you should make sure that all the settings are the same in both the Spectre simulator and Hspice simulator... and, maybe you need to set some initial conditions to make the circuit oscillate in Hspice.
Anyway, Hspice is always the golden standard in the IC...
measure input impedance cadence
(1). DC Rin and Rout: as what is said in the textbook, using a test voltage source to get the DC current, then R=V/I...
(2). Small signal Zin and Zout: just perform the S-Parameter simulation, no matter the simulator is Cadence or ADS.
Hope this helps.
Re: On postlayout simulation
Thank you all for the opinions. Here's something to add on my questions.
(1). Some guys working at some analog design companies told me that they usually do not perform the postlayout simulation at all (they're designing power management chips and LCD driver...
On postlayout simulation
Hi, the following two questions open to discussion, thanks.
(1). Is it indispensable to perform postlayout simulation for all of the analog circuits?
(2). I'm now using a 0.8um BiCMOS process to develop an anolog IC. While performing the postlayout simulation, I...
I think the second way will be more efficient, coz many different skills are needed in either circuit design or layout design. It could last a very long time for someone to develop and grasp both of them.
Re: Finding Layout Examples
Usually, the foundry provides the Pcell of the capacitor and inductor(if u r finding an example, they'll be a good one). In this case, all you have to do is to change the parameters.
OR you just follow the design rules from the foundry, and make ur own layout.
Has anyone ever verified the design with Nanosim and successfully taped out?
Nanosim has faster speed, but Hspice is always the golden standard. I'm really wondering which one I should use... :(
Pls give me some suggestions, thanks.
Re: how can i use hspice to simulate phase noise of oscillat
Synopsys has extended the Hspice to perform RF simulation. The Hspice with RF feature has been released already. You can have a try. (surely you should have the license of the HspiceRF feature first.)
BTW, spectreRF and ADS could...
Hi, I still get a little confused on this issue: "small signal models: linear; large signal models: nonlinear". May I say that the harmonics are all generated from large signal models?
BTW, what's the hspice level 49 model and BSIM model? one for BJT, one for MOSFET?