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  1. R

    IIP3 and 1db compression point(P1dB) of LNA

    I guess the question really is "why derivative superposition (DS) does not help P1dB?" DS is used to cancel out the 2nd derivative of transconductance, and the P1dB is also caused by this 2nd derivative (generally). So it should help both the IP3 and P1dB, shouldn't it? Any follow-up?
  2. R

    What's the cutoff frequency of TSMC 65nm process?

    Hi, I haven't used the TSMC 65nm process, I'm wondering what's the number of its fT (cutoff frequency)? Thanks, Ruri
  3. R

    Constant Gm bias circuit?

    constant gm circuit Always use off-chip resistor, if you wanna use the constant-gm bias in your design. --Ruri
  4. R

    Model file for capacitor.

    Hi, I think not every process provides poly-poly capscitors. Is it that your target process do not have the poly-poly capacitor devices? Do u have the PDK of the process you mentioned? Using the P-cells in the PDK will always be the preferred choice. Hope this helps. Ruri PS: I do have the...
  5. R

    How to design a current reference with zero TC?

    I think Zero TC is just like a wish, a TC about 10ppm might be more realistic. Ruri
  6. R

    Different results in Hspice and Spectre

    Re: hspice vs spectre Hi, I think you should make sure that all the settings are the same in both the Spectre simulator and Hspice simulator... and, maybe you need to set some initial conditions to make the circuit oscillate in Hspice. Anyway, Hspice is always the golden standard in the IC...
  7. R

    RF CMOS design model at 2.4 Ghz

    Re: RF Modeling As a matte of fact, the big problem you may face is not what you want but what you can have ... Yes, BSIM3v3.3 is good, however, few foundries are ready to provide. :(
  8. R

    How to measure Rout & Rin using Cadence Analog Design?

    measure input impedance cadence Hi, (1). DC Rin and Rout: as what is said in the textbook, using a test voltage source to get the DC current, then R=V/I... (2). Small signal Zin and Zout: just perform the S-Parameter simulation, no matter the simulator is Cadence or ADS. Hope this helps. Ruri
  9. R

    Three questions about post-layout simulation

    Re: On postlayout simulation Thank you all for the opinions. Here's something to add on my questions. (1). Some guys working at some analog design companies told me that they usually do not perform the postlayout simulation at all (they're designing power management chips and LCD driver...
  10. R

    Three questions about post-layout simulation

    Re: On postlayout simulation sorry, they're 3 questions :P
  11. R

    Three questions about post-layout simulation

    On postlayout simulation Hi, the following two questions open to discussion, thanks. (1). Is it indispensable to perform postlayout simulation for all of the analog circuits? (2). I'm now using a 0.8um BiCMOS process to develop an anolog IC. While performing the postlayout simulation, I...
  12. R

    Efficiency of Analog IC Designing

    I think the second way will be more efficient, coz many different skills are needed in either circuit design or layout design. It could last a very long time for someone to develop and grasp both of them. Rgs.
  13. R

    i have the lib for Hspice how can i apply it to ADS

    In the file menu, select import, then slect the netlist type: Hspice or spectre. I've done that many times, no problem at all. Good luck.
  14. R

    Looking for a beginners book for VerilogA and Ansys

    Re: Cadence in Unix If u wanna learn Cadence: https://www.ee.vt.edu/~ha/cadtools/cadence/cadence.html Verilog-A? Go google, huge stuff over there. Good Luck!
  15. R

    Looking for examples of on-chip analog inductor layouts

    Re: Finding Layout Examples Usually, the foundry provides the Pcell of the capacitor and inductor(if u r finding an example, they'll be a good one). In this case, all you have to do is to change the parameters. OR you just follow the design rules from the foundry, and make ur own layout. Rgs.
  16. R

    Howto install RFDE2003 under RedHat 9?

    Re: Howto install RFDE2003? Hi, as far as I know, RFDE2003 does not supported @ Linux. RFDE2004 does. BTW, did u get the PM from me? Thanks.
  17. R

    The comparison of Nanosim to Hspice

    Has anyone ever verified the design with Nanosim and successfully taped out? Nanosim has faster speed, but Hspice is always the golden standard. I'm really wondering which one I should use... :( Pls give me some suggestions, thanks. Ruri
  18. R

    how can i use hspice to simulate phase noise of oscillator?

    Re: how can i use hspice to simulate phase noise of oscillat Synopsys has extended the Hspice to perform RF simulation. The Hspice with RF feature has been released already. You can have a try. (surely you should have the license of the HspiceRF feature first.) BTW, spectreRF and ADS could...
  19. R

    question about PLL with separate gnd/vdd

    Hi, I have the same problem, could you pls explain a little more on the "nwell donut"? and will the voltage which tie the nwell to vdd affect the VCO or other high freq. parts on chip? Rgs
  20. R

    small signal model, large signal model?

    Hi, I still get a little confused on this issue: "small signal models: linear; large signal models: nonlinear". May I say that the harmonics are all generated from large signal models? BTW, what's the hspice level 49 model and BSIM model? one for BJT, one for MOSFET? Thanks.

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