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  1. DZC

    Is there any issue with this circuit?

    To correct the duty cycle of a 5GHz clock, I come up with the attached circuit. For 5GHz clock, R=10K and C=100fF. It works almost perfect according to simulation. But I just kind of worried, is there any issue associate with this scheme I have ignored?
  2. DZC

    Where is the EDA ebooks upload/download section?

    haven't login EDAboard and I found it missing? Is it still exist in this forum?
  3. DZC

    How to model a SERDES analog PHY with verilog?

    Hey ,guys, I got a task to built a verilog HDL (not veriloga) model for a SERDES AFE. This model will be provided for our digital guys to simulate. Anybody ever do this job? Would you plz show me the general procedure?
  4. DZC

    Problem with annotating in Spectre?

    spectre annotate My environment is IC5.10.41. I found it difficult to control the annotate status of the schematic. Occasionally it displays the right annotations as my choice, but most often it just annotate the Node voltage and can't be reset... Any good ideas?
  5. DZC

    How to modeling a SATA cable, plz?

    sata cable simulation I have the SATA RX and TX circuitm, and now I'd like to have a far end loop back test simulation. But I have no idea how to model the channel. Any suggestion?
  6. DZC

    How to implement a PLL lock detector?

    pll lock detector Is there any common used method?
  7. DZC

    How can I deal with 3rd HD in a 2nd SigmaDelta Modulator,plz

    I am designing a second order sigma_delta modulator for audio application. The input frequency is 8kHz and the sampling rate is 1MHz. The design target is 16bit but he simulated 3rd distortion of the SDM is as high as -54dB. The slew rate of the first OTA designed to be 20V/µs. What might is...
  8. DZC

    How to realize on-wafer test for a 4GHz clock?

    Hi, I want to buit a high speed Duty cycle corrector circuit. The process is 0.18um CMOS. The highest input and output clock frequency can be as high as 4GHz. On wafer probe test will be chosen. But I have no I idea how to built the I/O circuit. Can I just get rid of the ESD circuit or which...
  9. DZC

    A question on start-up circuit in biasing circuit, plz

    Paul Brokaw formulated the following practical rule: if on the circuit diagram one can draw a closed line around the supply bus that crosses only drains of MOS devices or collectors of bipolar transistors, then such circuit has the second stable condition when all components are off [106]...
  10. DZC

    Recommend some must-read papers

    These days I have a plan to read some papers in schedule,but there are so many papers in existance. And I believe there must be some papers you consider worthy reading,even must-read,especially those classic papers on general analog IC design theory. I will be appreciate if you would be so kind...
  11. DZC

    :?:How to clock such high performance ADCs?

    I found ADI have release the AD9461(16-bit,130Msps),also TI ADS5474(14-bit,400Msps). In sampling theory the clock rms jitter should be less than 50fs? Is there any equipment that can offer such low jitter clock? How do we generally clocking such high performance ADCs?
  12. DZC

    What is the component "SMN2" , "SMP2" an

    Refer to the Calibre LVS report as follows: Layout Source Component Type ------ ------ -------------- Ports: 19 19 Nets: 653 657 * Instances: 215 217 * MN (4 pins) 122 123...
  13. DZC

    I'd like to make make freinds from EDAboard.

    I am a graduate student. My research field focus analog IC design. Anyone wants to make friend plz join my MSN:asic_ant@hotmail.com:D
  14. DZC

    Some questions on Phase Detectors,plz!

    1.Since PFD can't achieve zero phase difference,just to what extend can it reach,say tens of picoseconds? 2.As far as I know the crystal oscillators works below several hundereds of Meg Hz,can I conclude the Phase Detectors also work below such frequency? 3.Is there any circuit to realized...
  15. DZC

    How do we usually get rid of clock skew?

    I've heard PLL,DLL and SMD are often utilized in such situation,but I'm not sure is it possible for a Phase Detector achieve the zero phase difference when the loop is locked. If it's possible what technique must be used? Thanks for your reply!
  16. DZC

    On Loading Data form Spectre

    I'm trying the script from cedence application note as follows: " out = outfile("./paramResults.out" "w") ; name the output file and open it for write access run() ; run the file results() ; open up the results selectResults(`tran) ; Select the transient results outputs() ; View the outputs...
  17. DZC

    About verilogA simulation

    Hi, I create a simple VerilogA model and use it within a transistor level circuit(a simple Inverter),but I found when I add the VerilogA module the simulation process become incredibly slow,and there are some warnnings too. Anybody having encountered such problem? Thanks for your reply.
  18. DZC

    How to implement a ultra jitter clock interface?

    Hi, I want to implement a circuit to carry the clock in the chip out of the chip. The jitter spec is less than 1ps and the clock frequency is 20M~500MHz. I'm considering to use the Current Mode Logic and the LVDS interface. My question is:does the LVDS interface capable of ensure such low...
  19. DZC

    Who have this Software?

    I'm not sure I put this post in the right forum,but ...:D I heard about a software nemed "ADDA" form a PHD thesis. I also searched from google and yahoo and find the link below, https://web.it.kth.se/~svante/free_software/free_software_index.html but it seems doesn't work any more. I'm very...
  20. DZC

    Any good papers on Pipelined adc Calibration?

    I found lots of them from IEEE,but is there any more classical papers or other documents worth reading?

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