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  1. V

    OFDM transceiver with rayleigh channel using Standard PDP in matlab

    I have built an OFDM transceiver with rayleigh channel using standard PDP's Like EPA,EVA and ETU.The problem is I am getting very high BER even for BPSK i.e 50-60 % or higher bits in error.Scatterplotting confirms it.My OFDM transceiver blocks include: ---- Random Data --...
  2. V

    Periodic placement of Pilot sequences in clusters

    Respected All, I need to design pilot based channel estimation which require optimal pilot placement.There are various schemes presented in literature but I am preferring Periodic Placement of Pilot sequence in clusters instead of sending all the pilots in a block.The problem I am facing is...
  3. V

    Matlab tolerance for a value that is Very very small i.e approximately Zero....

    Due to high Precision of MATLAB,it often treats values very very small i.e 2.4493e-15 not equal to zero that we usually interpret as zero in our calculations as well as programs.How is it possible in programming to cater these things during using Matlab functions?Is it possible to define our...
  4. V

    Semester project on schdeuling in Ad-hoc network

    Dear All; I am interested in doing a semester project of around 1.5 month duration on Scheduling in Ad-hoc network.Preferably i want to implement a scheduling algorithm and perform its simulation in MATLAB.Finally I can conclude by comparing results of adhoc network with or without...
  5. V

    uniformly distributed random number from 0 to 2*pi in MATLAB

    Rand generates uniformly distributed random values between [0 to 1], but I need values from [0 to 2*pi].Is there any method to explicitly force rand to generate values from above desired range instead of default [0 to 1]?.I had tried Angle = (2*pi) * rand(1,10) but not convinced.Any other...
  6. V

    Verilog HDL standard coding practices

    Dear all, As lots of books talk about inferring latches in hardware, when we miss few statements during coding like 1- not including else with if 2- not including default case with case statements.... but upon reading XST user manual examples I observed above are missings they not...
  7. V

    Manipulating character matrix into array in Matlab :

    Upon converting an input array into hex using Hex_LEN_INPUT = dec2hex(LEN_INPUT).My output appears as ... out = 0e68 1b59 2927 >> whos out Name Size Bytes Class Attributes out 3x4 24 char But I need my output to be as row vector like ... out...
  8. V

    [MOVED] My function to convert decimal numbers into binary numbers using Matlab

    To convert numbers ,I had written my own function in Matlab instead of dec2bin or bin2dec(because it returns strings).I had checked it for many test cases and found it working.Can any body confirm, it works for all the valid test cases.I mean to cater any logical mistake at this stage because I...
  9. V

    Matlab function 2 convert negative decimals to signed binary values

    Dear All, I need to convert signed/unsigned decimals to their equivalent signed binary values in Matlab.I had used 2 functions but they work for positive integers only i.e de2bi() and dec2bin().Is there any function that help me or I had to write my own routine for conversion. Regards,
  10. V

    begin end block and Non-blocking Statements

    Question 1: statements in verilog are executed in parallel but my question is What if we put them inside a procedural block? Begin Statement 1; Statement 2; end Now tell me in which order these are executed?both parallel or statement 1 then 2? Question2: If statements...
  11. V

    Clearing Block ram in verilog HDL

    I had made a dual port BRAM (separate port for read / write ).I want to add an input that clear the BRAM when its high.... How can I do this for 256 x 8 Bram so that my code is synthesis able and could be modeled in hardware/Technology....one approach is to use for loop but requires more...
  12. V

    Always Vs initial :stopping Simulation

    Dear, I know the difference b/w initial and always construct but I had found a bug during its use in stopping a simulation in Modelsim. 1- initial # 500 $stop; worked well and stops the simulation precisely at 500 time units. 2-always@* # 500 $stop; sets up an infinite loop and simulation...
  13. V

    ModelSim simulation Query

    On running a simulation if I had a check of stopping a simulation(say #200 $stop), test-bench code window popup with pointer to line #200 $stop .The problem is if at that moment I need to edit contents of test-bench code I will not able to do that even restart option not worked.Why ???But if I...
  14. V

    Projection Matrix function in matlab:

    Dear, The projection matrix P of any matrix A could be found by formula P = A*inv(A'*A)*A'; My question,Is there any built in matlab function that can give the projection matrix of any matrix... Regards,
  15. V

    floating to fixed point Qn.m format in verilog HDL

    A.o.a: In verilog HDL programming,I got some floating point arithmetic's to perform.I need to multiply a floating point number but problem is I am confused how to write verilog code that reads number convert it to fixed Q n.m format ....I know all the basics of Q n.m but problem is the...
  16. V

    Qn.m format for representing floating numbers as fixed point:

    Dear All, I need to know about the range of Qn.m format number for both signed and unsigned numbers, For example, I had 8 bits for representation of a number and format is Q3.5.what is the maximum and minimum floating point number that I can represent ?Give me a general formula for finding the...
  17. V

    Normalizing frequency for fir1() matlab function:

    Dear All, I am trying to implement an FIR band pass filter using fir1() function but I am confused in normalizing the frequencies.Whether I had to divide my frequencies by fs or fs/2 for normalization to be used as Wn. Which one will give me the correct results?I had divided my band freq...
  18. V

    How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim.

    Dear All, I am newbie and lastly I was simulating my own testbenches on Modelsim Simulator.Now I do not know the idea how to simulate my Verilog HDL testbench codes (not VHDL) in Xilinx ISE.I had already generated my waveform using test bench waveform editor in xilinx but i am interested in...
  19. V

    Histogram equalization hardware diagram for implementation in verilog hdl

    dear all, I know the working of histogram equalization algorithm, but i need to implement it in verilog HDL.The problem is that i am unable to draw the hardware level diagram/design of algo but i am sure i can implement it on HDL once i got the working diagram. Can anyone give me the hardware...
  20. V

    carry lookahead generator

    Dear All, I had written a verilog hdl code for carry lock ahead generator.The equations for generate,propagate,carry and sum are implemented through for loop using gate level as well as behavioral level.If anyone can tell that my code is professionally ok or any modification still required. I...

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