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I have question about how to choose vdd and temp in SF and FS (slow-fast and fast-slow) corner in hspice
In case of SS, I choose VDD = 0.9 * VDDnom and temp = 125
In case of FF, I choose VDD = 1.1 * VDDnom and temp = 0
I have a question how to convert a circuit from old technology to new technology.
Let say I have a bandgap design using 250nm technology and want to design to 180nm. How I can do it:
Do I have to design from beginning using 250nm schematic?. Assume both process bandgap take out 1.2v...
I want to mount a secodary hard drive in scientific linux:
This is information of hard drive when i type fdisk -l
Disk /dev/sdc: 1000.2 GB, 1000204886016 bytes
255 heads, 63 sectors/track, 121601 cylinders
Units = cylinders of 16065 * 512 = 8225280 bytes
Sector size (logical/physical)...
I have a question in designing 4 bit flash adc.
How to choose resistor value in resistor ladder? When I change resistor value I see output of compartor has wrong comparation. The strange thing here is if I run compator alone it works well. Does value of resistor ladder affect comparation?
Anyone know how to measure dnl, inl of adc please show me how to do ? From what I know, we ramp up input of adc (slow ramp) in hspice and import result data to matlab to get dnl, inl.
Thanks a lot
Im desinging 2 stage fully differential opamp with continous cmfb. My design using smic18mmrf with VDD=3.3v and input cm = output cm = 1.65v. I test transient with apply sin wave 20uV peak to peak
to see how output behave. From the waveform (see attached) , the output distortion at below...
I am simulating slew rate of fully op amp. I set up as the way in picture below and simulatiion look ok, but I have a question about resistors value in simulation. How to decide value of resistor value? If R too large the current from vin to input of opamp will be 0 ---> the set up...
Im designing fully differntial folding cascode opamp and my opamp has: gain = 70dB, phase margin = 80. When I test for overshoot and setling time I see a 20mV overshot but the worse is taking long time to settle. Anyone can give a suggestion how to fix this.? Thanks a lot
I have problem creating hspice netlist from Cadence ADE virtuoso 615. When I open ADE window --->simualtion-->Netlist--->Create. I can not click on any subtree under Netlist (Create, Display, Recreate) . If anyone has this problem before please show me how to solve it. I install cadence on...
Im confusing with LDO quescent current of LDO. Some one define it is current of power transistor w/o load. Some define it is total current (Ivdd) of LDO + bandgap + current bias. I see some paper tells quescent current around 7uA, and LDO can handle up to 100mA loading. From my...
I am installing HSPICE2010 in linux system today. When I tried to execute hspice command it shows the errors
Checkout request rejected by vendor-defined checkout filter Feature
I spend 2 hours try to figure out the problem but no help. Anyone has experience with this problem please help...
Any one has experience to bias fully differential folded cascode op amp without cmfb? It took me a lot of time to make each transistor in saturation. I know with cmfb you can make it more saturation easier. Please let me know your suggestion. Thanks a lot