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    Script to find probe pads location in cadence virtuoso layout

    Hi all Anyone know how to write script to find probe pads location in cadence virtuoso ic layout? Thanks
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    How to do dc sweep 2 variables input in cadence spectre

    Hi all Anyone know how to run cadence spectre with sweeping 2 input variables? Let say sweep vgs and vds of nmos Thank your
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    How to probe hierarchy signal in cadence spectre

    Hi all Anyone know how to probe hierarchy signal in cadence spectre? I only know how to probe signal on the top only. Thanks a lot
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    How to choose VDD and temp in hspice corner

    Hi all I have question about how to choose vdd and temp in SF and FS (slow-fast and fast-slow) corner in hspice In case of SS, I choose VDD = 0.9 * VDDnom and temp = 125 In case of FF, I choose VDD = 1.1 * VDDnom and temp = 0 Thank you
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    How to convert a circuit from old technology to new technology

    Dear all I have a question how to convert a circuit from old technology to new technology. Let say I have a bandgap design using 250nm technology and want to design to 180nm. How I can do it: Do I have to design from beginning using 250nm schematic?. Assume both process bandgap take out 1.2v...
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    mount a second hard drive in scientific linux

    Hi all I want to mount a secodary hard drive in scientific linux: This is information of hard drive when i type fdisk -l Disk /dev/sdc: 1000.2 GB, 1000204886016 bytes 255 heads, 63 sectors/track, 121601 cylinders Units = cylinders of 16065 * 512 = 8225280 bytes Sector size (logical/physical)...
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    4 bit resistor ladder flash adc

    I have a question in designing 4 bit flash adc. How to choose resistor value in resistor ladder? When I change resistor value I see output of compartor has wrong comparation. The strange thing here is if I run compator alone it works well. Does value of resistor ladder affect comparation? Thanks
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    How to measure adc dnl inl

    Hi all Anyone know how to measure dnl, inl of adc please show me how to do ? From what I know, we ramp up input of adc (slow ramp) in hspice and import result data to matlab to get dnl, inl. Thanks a lot
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    2stage fully differential opamp output distortion

    Hi all Im desinging 2 stage fully differential opamp with continous cmfb. My design using smic18mmrf with VDD=3.3v and input cm = output cm = 1.65v. I test transient with apply sin wave 20uV peak to peak to see how output behave. From the waveform (see attached) , the output distortion at below...
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    Any software to convert pcboard layout to schematic

    Hi Do anyone know software can convert pcboard layout to schematic? Thanks
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    CMRR of differential op amp

    Hi all Im checking CMRR of full differential opamp. From what I know CMRR = Ad(dB) - Ac(dB). I got Ad(dB) = 65dB and Ac(dB) = -27dB ---> CMRR = 92dB? Ac(dB) < 0 is correct? Thanks a lot
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    Fully differential op amp Slew Rate

    Hi all I am simulating slew rate of fully op amp. I set up as the way in picture below and simulatiion look ok, but I have a question about resistors value in simulation. How to decide value of resistor value? If R too large the current from vin to input of opamp will be 0 ---> the set up...
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    Overshot and ringing of fully differential opamp design

    Hi all Im designing fully differntial folding cascode opamp and my opamp has: gain = 70dB, phase margin = 80. When I test for overshoot and setling time I see a 20mV overshot but the worse is taking long time to settle. Anyone can give a suggestion how to fix this.? Thanks a lot
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    Calculate S/H sampling rate from waveform

    Hi all I calculated sampling rate from S/H waveform is 200Ms/s . Is it correct? Thanks BTW: The time scale in nanosecond (ns)
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    Cadence virtuoso IC615 can not extract hspice netlist

    Hi I have problem creating hspice netlist from Cadence ADE virtuoso 615. When I open ADE window --->simualtion-->Netlist--->Create. I can not click on any subtree under Netlist (Create, Display, Recreate) . If anyone has this problem before please show me how to solve it. I install cadence on...
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    Quescent current of LDO

    Hi all Im confusing with LDO quescent current of LDO. Some one define it is current of power transistor w/o load. Some define it is total current (Ivdd) of LDO + bandgap + current bias. I see some paper tells quescent current around 7uA, and LDO can handle up to 100mA loading. From my...
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    Flexlm license problem

    Hi all I am installing HSPICE2010 in linux system today. When I tried to execute hspice command it shows the errors Checkout request rejected by vendor-defined checkout filter Feature I spend 2 hours try to figure out the problem but no help. Anyone has experience with this problem please help...
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    [SOLVED] Small Signal of operation amplifier

    Hi Any one know how to do transfer function Vg(s)/Voe(s) of this op amp without drawning small signal. I know some one can do this quick but I do not know the trick. Thanks
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    Fully differential Folded Cascode op amp bias

    Hi all Any one has experience to bias fully differential folded cascode op amp without cmfb? It took me a lot of time to make each transistor in saturation. I know with cmfb you can make it more saturation easier. Please let me know your suggestion. Thanks a lot
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    [SOLVED] Measure close loop gain op fully op amp

    Hi Can anyone help me how to measure close loop gain of the op amp in the picture in hspice simulation. Thanks

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