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Hello All ,
I am designing a module that has to run at 350MHz. I am in the architecture phase and would like to know how to figure out the possible frequency of operation of the design before entering the synthesis phase. Normally we have to wait till the synthesis to get an idea about the...
What could be the optimal buffer for an asynchronous FIFO with the source clock
at 50 MHz and the Read clock is 25 MHz
Data is clming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latancy also into account.
Sometime Back i read a comprehensive paper that described about 10 Best ways to code an FSM in Verilog and VHDL for time /Area Or both.
It is like 3 Process/ 4 Process/Huffman style coding ..
I forgot the name of the paper or the chapter or book.
Anyone has similar document pls...
I have one question regarding the Metastability. Lets suppose that the design has suffered metastability . What could be the Symptoms in the Hardware that make us believe that is has suffered the metastability.
Any past experience with someone regarding this...
I am wondering as what considerations one must take to declare the path as False path. We know that the paths between two different clocks/Clock groups are freated as false path ans is not considered in the STA analysis.
Anyone has some guideline for defining the False path in the...
Can anyone describe the setup and Hold time at the transistor level. Why Setup /Hold time is needed i mean its genesis. We know that when either of them is violated it leads to metastability.
It will be a good discussion to find out at the transistor level how it works and from where this...
I am implementing the I2C Slave and i am using to data lines for sda input and sda output.
MY question is that shall I expect from I2C bus to give me Z as input in place of 1
Shall I drive output 1 as Z to the sda_out
i2c start condition setup time
I have to detect a case when the SCL is high and the data changes from high to low then it is a START condition and when the SCL is high and data changes from Low to High then it is a STOP condition. Henceforth My design and the code is clocked at SDA_IN
I am implementing the I2C Slave and I am using the I2C clock SCL for
detecting the start and stop condition . I am detecting the start and
stop successfully in simulation but i am not able to do the same in
the post synthesis scenario. More so I am getting a setup time...
As I understand from you post the answers to your questions are below.
You have downloaded the VHDl files for the Encryption algorithm .You will find that there will be a top level file that binds all the modules in the design. In VHDL we have top level ENTITY that has...
VXI bus interface design
I am desiging a VXI interface design on FPGA.
Can anyone hep me if they have previously designed an interface / The programming language is VHDL.
It will be a great help if some has done it previously could give me some heady way to go ahead with the...
I am in a project where I have to select an FPGA for the project. It may be Altera/Xilinx.
I am new to this process of selection .. Can anyone help me in giving some document citing the FPGA selection guidelines so that i will be able to do the right choice.
i am trying to write a procedure in VHDL which i want to generate clock and on the rising edge of the clock i want to shift data on the rising edge .
When i use the clause Rising_edge(clk) it is not doing anything and no output is seen ..
Can anyone help as how to generate a clock...
To set the system clock under Linux, use the date command. As an example, to set the current time and date to July 31, 11:16pm, type ``date 07312316'' (note that the time is given in 24 hour notation). If you wanted to change the year as well, you could type ``date 073123161998''. To set the...
In reply to Avi I have to make a point as FIFOs are used to match the data rate across the clock domain when we use async FIFOs. But in the case when the data rate is dame and clck phase is different then we have to use b2g converter and once the gray code is sucessfully obtaimed in the...