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Re: CLOCK GENERATION
you can get it in google. or try in search engines.
I know the paper which will provide you complete details regarding clock dividers and pll
"clock divider made easy" topic search in google and you will get the link for download
developing verification environment in verilog
I have to develop a system verilog verification environment for my project.
could u plz help me out in this regards,and also provide some tool knowledge
and reffer some website form which i can download some materials.
fifo question 80/100 8/10
One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of...
Re: regarding cycle based symulators and event based symulat
cycle based simulators are usefule for synchronous designs where operations happen only at active clock edges works on cycle by cycle basis.timing information between two clock edges is lost.
Re: signatur analyse
signature analysis is a way of testing your design.
In this you have to give psuedo random sequence of 1's and 0's to your design and notedown the output bits. this is chips signature.
when you are giving the second time same sequence it should give the same output.
fix hold time violation
whhen setup time time violates your design works with lesser frequency but when you hold time violates your design doesnt work at all.thats why hold time fixing is critical.
You can fix setup time time by adding some dalay by adding register or you can adjust the verilog...