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  1. R

    drc error in cadence--hot nwell

    hot nwell hai, i am getting DRC error as HOT NWELL while running drc for any circuit in cadence VIRTUOSO layout editor. how could i rectify this.
  2. R

    preamp used in comparators

    reduce kickback comparator in comparators(latched comparators) very low gain pre-amplifiers are used . what is the use of this pre-amp.
  3. R

    analog layout materials for beginners

    hai, i have started drawing layout using cadence for Comparator.tell me where to refer for this. possible send me some books or some materials for this.
  4. R

    gain of dynamic latch comparator

    i am not able to increase the gain of the pre-amplifier stage beyond 2V/V. is this gain sufficient for the design. gain is low because the load for M1 and M2 transisters are in trode region(according to the design). how can I design the dynamic latch.
  5. R

    problem running LVS in Cadence

    disk quota exceeded cadence I get problem called "unable to build VDB file" while running LVS in cadence virtuoso. what does it mean and how can i oversome this.

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