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  1. S

    can increasing overall frequency help in saving GATECOUNT?

    hi all can increasing the frequency improve with reducing the GATECOUNT of the design , iam a newbie , i dont know if it is a proven strategy , can anybody explain me how ? thanks in advance
  2. S

    any good strategy to analyse RP groups and Macro placement

    hi , any good methods/strategies or things to keep in mind for the placement of big cell groups like EBB's and RP's ?? thank you
  3. S

    any method to count flylines

    hi i want no of datapaths going out from EBB's .. iam checking with flylines , is there any way to count the no of flylines going to some particular logic ....iam using IC compiler btw thank you in advance
  4. S

    The command for creating placement bounds of a particular unit in ICC

    what is the command for creating placement bounds of a particular unit in ICC??
  5. S

    What is the half cycle datapath ?

    hi all , can anyone explain what is a half cycle datapath ?? thank you
  6. S

    ILM - interface logic models

    hi , how to use an ILM ?? does ILM help in easing the dataflow analysis ?? pls help
  7. S

    rp group co ordinates

    hi all , whats the command in ICC to get the RP group co ordinates ?? thanks in advance
  8. S

    saving gatecount in the design

    how to save gatecount in our design ?? can we discuss some strategies
  9. S

    help in dataflow analysis in ICC

    how to list all the paths going from a port in ICC ?? urgent help required pls thanks in advance
  10. S

    tcl script to get logical path from EBB's

    hi guys, iam a newbie in VLSI design , in my design i have moved my EBB's (macros), now i want to analyse the effect of EBB's on routing and timing , i want to write a script for checking the fanout and the tracing the logical path for all the pins connecting EBB , i have only basic background...
  11. S

    transistors in linear region

    i have a circuit with as many as 8 transistors in the linear region, how to analyse these transistors without small signal model how to decide W/L ratios for these transistors ? any suggestions plz, thank u
  12. S

    analog multiplier topology

    here the 4 PMOS transistors are in saturation and all other NMOS transistors are linear. can anybody explain me how this multiplier works ? if anybody could explain it with equations it will be really helpful well the o/p is taken as vo1-vo2= (kp/(kn*km))*(xy) [/img]

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