Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. I

    can we Convert miliway *.tf file into cadence *.lib???

    Hi , I want to convert my milkyway *.tf library files in cadence generic *.lib formtat to run on RC. Is there any way to do this conversion? Thanks, Saurabh
  2. I

    Difference between Endcap/Decap/Filler cells (Structure wise)

    I got exact answer as follows, Main difference between Endcap cell is they have dummy poly. which Dcap or fillers does not have. SO it prevents any stress or DRC violation on actual circuit and design while fabrication. Have not seen actual layout of standard cell, will reply again after...
  3. I

    Difference between Endcap/Decap/Filler cells (Structure wise)

    Okay ..So why cant we use filler cells as end cap cells or vice versa. Why do we need special kind of cells as Endcap cells?
  4. I

    Difference between Endcap/Decap/Filler cells (Structure wise)

    Hi, I know there are multple threads about this question. But did not find what was I looking for, I know Endcap at the end of rows and around macro, Fillers in between design to fill the gaps n well continuity, and Decap for IR drop to give exra capcitance... My question is what End cap has...
  5. I

    Skew and insertion delay

    Hi, Let me put this in simple words... So whatever green an red is there is insertion delay. which is mainly due to latency from source of clock. Now Skew is due o unbalance clock tree... The difference between capturing clock latency - launching clock latency = skew having said that, we...
  6. I

    verilog simulation in cadence

    Hi, Try this tutorial. https://www.scribd.com/doc/277287588/Cadence-Tutorial-New#scribd
  7. I

    Setup and hold time in same path and on the same flop ?

    Hi, Setup and hold can occur same time on same flop.... if the path is different. Having said that in ideal scnario it can even occur at same path... if frequency operation is not calculated correctly... But this is hypothetical answer... practically it's difficult. Saurabh
  8. I

    extraction of spef using star rc

    Hi, To get spef you need following inputs, 1) complete DEF (logic with connection) 2) You dont use just .tf (is has only cell delays) as this is routed design you use technology file to get real data values of metal and vias aloang with fanout and actual routing delay. 3) RC corners with PVT...
  9. I

    details about OCV and AOCV

    Hi, OCV value usually comes from CHIP vendor after doing multiple simulations, legacy design data and scaling factor. (TSMC, GF). Generally derate values vary from 5 -10% depending upon your chip, design, application and technology. f you are top level designer, you should know your Temp...
  10. I

    high performance and low power

    Hi, when you mean by high performance.... there are many other aspect to it. Such as: power, timing, size and most of them contradict to each other. Like there is compromise between speed and power. (current trade) If you are newbie : Think about the best performance car: it may be high speed...
  11. I

    cadence encounter command line documents

    Thanks Dapul, But what I am looking for basic commands of cadence encountre such as dbget, addvia whic we always do by tab key. If anyone has tutorial or manual please let me know. Thanks!!!
  12. I

    cadence encounter command line documents

    Hi, Does anyone have any documents on cadence commands for command line. I am looking for any pdf or ppt for the same. Thanks!!!
  13. I

    DDR PHY Infromation???

    I need understanding of DDR PHY... NI idea about the difference between (DDR for computer SDRAM's or Graphics DDR ) these to PHY ... Can you give me basic architecture of any DDR PHY ... I have tried https://www.ddr-phy.org but did nit find any useful information about basic architecture!!!
  14. I

    DDR PHY Infromation???

    What is DDR PHY???? Where can I get information about DDR PHY, its architecture, and operation???? Any input will be helpful. Thanks!
  15. I

    Grey, Meyer Analog IC design Ebook

    analog integrated circuit design grey, meyer, hey now i need the solution manual for design and analysis of analog integrated ciruits 4th edition........... where can I get it?
  16. I

    Problems for practicing MAGMA scripting

    MAGMA Scripting so you have any idea of ticlke? or you can also work in perl

Part and Inventory Search