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As I know, the command to create Interface Logic Model (ILM) create_ilm in ICCompiler 2017 version was obsolete.
Do you know that is there equivalent command to substitute for create_ilm, or the functions of ILM are completely removed and are already included in CEL view an FRAM view...
I installed Virtuoso 6.14 and worked fine, and now I go on installing SOC Encounter 62
But when start to run command "encounter", the following error:
This version requires license using cdslmd daemon
Checking out Encounter license ...
Fail to find any Encounter license...
When I run Virtuoso, there is one error in CIW window like that:
*Error* load: can't access file - "/home/eda/cadence/ic614.hotfix/tools.lnx86/dfII/home/eda/synopsys/hspice_vE-2010.12/hspice/hspice.ini"
DO you know how to fix it, how can we configure location of hspice.ini to avoid this...
Thank you, yx.yang,
As your mention, in my case, there are timing violation due to design rule. This is a result after running IC Compiler. In case that slack values are less than 0, we can use fix_eco_timing and write_changes to generate ICC TCL to fix, but in report timing file there are no...
I did timing verification with PrimeTime. After the report_constraint, there are some violations as below
report_constraint -all_violators -verbose
- Capacitance 1.01...
I have encountered an error with IC Compiler.
When I open a cell from a library, there was an error:
"cell is locked by pcname (pid 1234 server) check again ..."
I run command ps to list the thread and try to use command kill 1234, but the pid 1234 is not available.
Please help me how to...
I want to change the VHV (Vertical - Horizontal - Vertical) routing styles to HVH (Horizontal - Vertical - Horizontal) routing styles in IC Compiler.
How can I modify ? In technology file ?
Thank in advance
I am designing a chip with a TOP level chip and many instances inside.
I synthesized and converted the sub designs to CEL layout by IC Compiler.
Now I want to place and route a TOP level which contains those sub designs in hierarchy design.
I included layout sub designs in...
I am running Design Compiler for synthesis the following code, but I have encountered this error
Error: m4k.v:58: invalid symbol single_onehot found in activation expression. (VER-254)
Error: m4k.v:58: Illegal reference to memory single_onehot. (VER-253)
reg [63:0] onehot...
Because I have the technology file and library file from Astro, but now Astro is not available, the equivalent tool is Astro. I am using a technology and library file from Apollo in Astro. After I create library, add library reference, export CELL from synthesis netlist, then I create...