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  1. E

    Running CORTEX-M0 using 8bit SRAMs

    Hi all, Is it possible to run CORTEX-M0 (which has a 32bit data bus) using an 8bit SRAM ? If possible, the method would be the following, right? Method: a memory controller has to be used(built) that operates as a AHB-Lite slave. Furthermore it has to use wait states to read 4 bytes to built a...
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    Accessing IOs and other peripherals when running WinCE on ATMEL ARM9

    Thanks so, no drivers are needed and accessing GPIO can be done via WinCE APIs ?
  3. E

    Accessing IOs and other peripherals when running WinCE on ATMEL ARM9

    Hi, I've got a few questions about using WinCE on an ATMEL ARM9 microcontroller: Is it possible to access the IOs (and/or their interrupts) when running WinCE on a ARM9 Microcontroller (ATMEL) ? Do I need to write device drivers for WinCE to access the IOs? How about other peripherals such as...
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    Solid State Drive for SATA port using microSD cards

    It is possible, but you need to implement the SATA functionality in you uController. The most important attribute of SATA is its speed. If you're intending to do such thing, then be sure to meet the minimum requirement by SATA. In fact, you migh be needing something more than a uC, like a...
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    ldpc decoder implementation-reg

    Hi, 'Real' type in Verilog is not synthesizable. If you really need to handle 'real' values then it is possible to use the IP-Cores that provide functions on 'real' values, for example addition,multiplication, square root,... There are many free IP-Cores for that matter... The other option is...
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    ADC interfacing spartan 3e

    Hi, Your question is too general. There are different ADC interfaces which require different handling. ADC's output can be available as parallel, SPI or other forms. You need to specify the ADC interface and then read the datasheet in order to get the output samples. After that, there are...
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    Accessing IOs and Interrupts on ARM9 and WinCE

    Hi, I've got a few questions about using WinCE on an ATMEL ARM9 microcontroller: Is it possible to access the IOs (and/or their interrupts) when running WinCE on a ARM9 Microcontroller (ATMEL) ? Do I need to write device drivers for WinCE to access the IOs? How about other peripherals such as...
  8. E

    [SOLVED] Is it possible to layout a BGA484 on a one layer PCB?

    Thank you, My question was the possibility of mounting a BGA484 rather than the EMC an SI issues. I am already convinced to use the multilayer boards. However, here are the info that were missing: The IC is one of the Actel's low power FPGAs : M1AGL1000 The clock oscillator will produce a 5MHz...
  9. E

    [SOLVED] Is it possible to layout a BGA484 on a one layer PCB?

    Thank you very much, you really did help me. but one question, "tens of amps" ?! isn't it probably tens of miliamps?
  10. E

    [SOLVED] Is it possible to layout a BGA484 on a one layer PCB?

    Thank you very much, It is not a high speed board (maximum clock freq = 50MHz). But if, for what ever reason, I am obliged to use the one-layer board then in order to connect tracks to the IOs (BGA) I should use some through-hole vias beneath the IC surface, right?
  11. E

    [SOLVED] Is it possible to layout a BGA484 on a one layer PCB?

    Hi, Is it possible to layout and assemble a BGA-484 IC on a one-layer PCB (only two signal layers and no image planes)? If possible, is it a good idea? Thanks very much
  12. E

    Making a big multiplier from two smaller ones

    Hi, I'm supposed to design a 24*12 signed two's complement multiplier. Furthermore I am supposed to do it using ONLY two 12*12 multipliers (both are signed two's complement multipliers.) The problem is that the multiplication operation is signed. In a rather simple approach I -determined the...
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    How to implement a specific MCU/CPU in FPGAs?

    Hi, I'm reading this thread long after it's started and the link you provided is not working anymore. Would you please send that material (about cpu design) to me? my email addr : sepehr.ameli@gmail.com Thank you very much in advance.
  14. E

    A question for implementing Cryptographic algorithms

    probably, if the irreducible polynomial is always constant, then there's no use keeping it in a register (in fact the synthesis tool converts the constant number into hardwired logic). If there is a register for keeping the irreducible polynomial, then it must be changed or update sometimes...
  15. E

    A question for implementing Cryptographic algorithms

    Hi, Implementing finite field multiplications, is all about resource and performance optimization. In many different applications, one multiplicand is always a constant number (i.e a constant member of the specified finite field) so the general form of that Anyway, no one can fit five bits in...
  16. E

    Adding APB bus in Libero IDE

    thank you, that's what I needed ;)
  17. E

    Adding APB bus in Libero IDE

    Hello everybody, My question concerns Libero IDE 9.1 : Is it possible to add an APB (or AHB) bus interface to a user defined HDL module which is recognizable by the 'Auto Connect' command in canvas? I've seen an Application Note regarding this issue but the device used in there was a Fusion...
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    FPGA Low Power Design : Clock Gating or Asynchronous Reset

    so you confirm that keeping the asynchronous reset asserted cuts the clock tree at primary levels (so little power is consumed compared to not asserting the reset) ? do you also confirm that this method is better than simply gating (ANDing) the clock in low speed designs?
  19. E

    FPGA Low Power Design : Clock Gating or Asynchronous Reset

    Thank you for your interest. The ADC supports the FPGA with samples at a rate of 500 samples/sec FlashFreeze is a state (supported by some of Actel FPGAs) that the device retains it RAM and register content and still consumes very little power. This mode is activated by FlashFreeze Pin. Every...
  20. E

    FPGA Low Power Design : Clock Gating or Asynchronous Reset

    you're right, it's CoreABC while the CoreABC is disabled the other modules store ADC samples to be further processed and then it CoreABC's turn ... the device does goes to FlashFreeze mode but at other phases of system activity...

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