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  1. K

    Looking for references about grounding

    Has anyone any good reference/source where I could find some answers in following grounding issue: My metallic chassis contains three different PWB boards: PSU, digital card and analog RF card. How should the grounding be organized. To connect the RF card and digital card in multiple places to...
  2. K

    How to define or calculate the DAC output noise floor?

    How to define or calculate the DAC output noise floor? The intention is to produce 100 MHz real IF out of the DAC. I would need to konw the noise floor, since it affects the noise level at antenna. Is there a specific parameters in the DAC datasheet from whic I could calculate the noise floor?
  3. K

    wideband signal power

    Hi In case I have 10 MHz wide RF signal and I have measured the power level with spectrum analyzer (RBW=100 kHz), so what is the total signal power? The signal power level in the spectrum analyzer screen is -30 dBm. Can anyone explain this explicitly?
  4. K

    Calculating the mu parameter for a 2-port device stability

    When calculating the unconditionally stability of a 2-port device, is it enough to calculate the mu parameter (mu>1 => unconditionally stable) or do I have to calculate as well the accompanying parameter mu' (or mu_prime) and also see if that is >1? Or is the case so that whenever the mu>1, the...
  5. K

    Residual FM (VCXO vs VCO)

    I have made some comparison measurement between (VCO / VCXO) based PLL synthesizers. I got a bit contradicting result. At the same operating frequency 400 MHz, the VCXO based synthesizer has much better close-in phase noise (as expected) BUT the phase noise analyzer claims that the VCXO based...
  6. K

    How to measure a mixer group delay ripple with vector network analyzer?

    Can anyone tell how to measure a mixer group delay ripple with vector network analyzer? I need to make a vector measurement plain scalar measurement is not enough thanks in advance.
  7. K

    VBW setting in spectrum analyzer

    vbw spectrum Hi, Is there any rule of thumb what kind of video bandwidth I should use for a certain resolution bandwidth? Does this rule apply to all measurement cases or is there multiple rules (for example when measuring with zero span etc.) Any good references in this issue?
  8. K

    Synthesizer frequency stability

    frequency stability of synthesizer Hi all, Does the long term frequency stability of a synthesizer depend on completely of the accyracy and stability of the PLL reference frequency? So that the loop filter design and the VCO itself does not affect on the long term stability (it is assumed that...
  9. K

    LO harmonics effect on FET mixer

    Hi all, Could some one give me an answer about how does the even order harmonics of strong LO signal affect on FET mixer? Does the second order harmonics cause performance degradation? Of course they will produce mixing results but does they affect on the output signal quality on the...
  10. K

    sinewave clock to square wave

    diode 1ss99 Hi, I need to convert 250 low jitter sine wave clock to square wave or so called clipped sine wave. Could anyone propose suitable circuitry. I'm thinking of using fast diodes to clip the sine wave, but so far the signal shape has been something else than clipped sine, more like a...
  11. K

    Amplifier phase noise

    What factors do affect the buffer ampliifer phase noise? In Lo chain, I have several buffer amplifiers in cascade. If I want to minimize the amplifier chain effect on synthesizer phase noise, what kind of amplifiers (technology?) I should choose? Low NF amps or what. LO buffers usually are...
  12. K

    Does DSB or SSB mixer generate LO frequency harmonics internally

    Does DSB or SSB mixer generate LO frequency harmonics internally? Meaning if I feed sinusoidal LO, will there be mixing results of RF+2LO or RF-2LO
  13. K

    Frequency accuracy (synchranization)

    How do I interpret this: The allowed system clock and RF center frequency error in normal synchronized mode is +/- 2ppm. If system clock is 100 MHz anf RF carrier is 3 GHz, does this mean that RF carrier can deviate +/-2 *10^6 *3 GHz = >+/- 6kHz Or how should I understand this requirement...
  14. K

    LO chain effect on VCO pulling

    Hi, My VCO has a pulling characteristics of 4 MHz pp @ 12 dBr, If my LO distribution chain has reverse isolation like -70 dB, how can I calculate what is the pulling effect at VCO output. So if the load changes at the end of the LO distribution chain, taking into accoutn this 70 dB isolation...
  15. K

    Need spreadsheet for system spur analysis

    Hi, Has anyone a suitable excel spreadsheet template for system spur analysis? I would need to take into account tunable LO, RF, IF, reference frequency and system clocks. It would help if someone could provide me such spreadsheet template. Anyway, I guess the analysis is quite straightforward...
  16. K

    jitter spec for DAC clock?

    I need to specify the clock jitter requirement for baseband DAC which transmits 50 MHz BW signal (centered around zero frequency) it is 16 bit DAC. If someone could help me to find some equations to calculate the clock jitter spec. It is of course dependent on the desired SNR but should I...
  17. K

    Explanation of the residual FM concept

    Hi, If someone could explain the concept of residual FM? If I have very small RMS integrated phase error calculated from phase noise curve, does it automatically mean that also residual FM is small? Or is the requirement for low integrated phase noise somhow in contradiction to get low residual...
  18. K

    RMS phase error conversion

    rms phase error Hi, If someone could help me on this. How to convert the RMS phase error calculated from synthesizer phase noise curve into dBc value?
  19. K

    LO buffer influence on phase noise

    I have made RF LO with some PLL and VCO (+loop filter). The output of the synthesizer is about 0 dBm. I want to buffer it up to +17 dBm for passive mixer. Does anyone know how does the amplifier affects the phase noise? Any references? Thanks in advance
  20. K

    resistive non symmetric power divider

    Does anyone have good design guide how to design unequal resistive power divider. Is it possible to get good match in every port? The losses does not matter in this case.

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