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    Embedded system master in Egypt

    Here it is : https://www.nileu.edu.eg/school_of_eng.htm But please if you found that this program suits you, make sure that it is quite a good program and try to get in contact with other students who are already involved in their programs to build a vision of how good is the university. What...
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    Embedded system master in Egypt

    Hello, Do you want M.Sc. in Embedded Systems Design --> Microelectronics... If so I know that NILE UNIVERSITY will be offering M.Sc. and M.Eng. in Microelectronics but I don't know how good is the university and the program are... It will start for the first time in the university. Regards
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    Best TV Comedy series

    "Seinfeld" rocks
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    How to identify whether it is DVB, ATSC or any other stream?

    Re: DVB Hello, Aren't the DVB and ATSC considered two different standards ?
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Hi, Here is a do file under the name "do.do" ; it includes all the commands including those that force the signals. So add this file to the folder including the design. and then use the command : do do.do and check your wave window.
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    Which simulator and compiler support System Verilog?

    Re: System Verilog No Simulator Supports all the SV features , but what I said is that ModelSim is the one Simulator that supports MOST of SV features.
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    Which simulator and compiler support System Verilog?

    Re: System Verilog Hi, I know that ModelSim supports most of the SV stuff - whether its design or verification- and you can check the TechNotes to know to what extent is the SV supported. ModelSim PE student Version (Free Version) : SV design and Verification (Parts ; Assertion Based...
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Ba3d ma 3endakom ya Salma :) and you are WELCOME
  9. W

    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Here is what i done ...... use these commands: vcom DFF_CLEAR.vhd -pslfile DFF_CLEAR_TB.psl vsim dff_clear -assertdebug view assertions Then try to force the signals using the ModelSim GUI .... instead of a testBench and here is the view i got.
  10. W

    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Hi, *Why don't you list the ModelSim commands you are using and upload the design? *What ModelSim version, are you using ?
  11. W

    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Here it is , but it is some how BIG. The Instructions are in a file "doit.sh", so if you have linux or Cygwin on windows just use "doit.sh demo" ... otherwise just open the file and u can find the ModleSim Instructions. Its one of the ModelSim examples so you can find it...
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    ModelSim Problem: Licensing error

    how to resolve modelsim set back date problem It happened once for one of my friends, and the only thing that could be done was to re-install WXP and ModelSim. So don't you have an image or a restoring checkpoint ?
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    SystemVerilog simulation in Questasim 6.2b ?

    these features are only supported in questasim. What i figured that you get this message only if the continuous assignments are inside a generate block. However, when i ran a simulation the results were ok.
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    SystemVerilog simulation in Questasim 6.2b ?

    systemverilog svchk Hi, Can you send the file which gives you this warning .. ?
  15. W

    Beginner books about Image processing

    Re: book for beginners Digital Image Processing for Gonzalez is Good.
  16. W

    Recommend me a PIC Compiler

    Re: PIC Compiler The limitations are made after 60 days of using C18 , Note that we didn't use much of the options that were limited but , one of them was very important "The Code Optimization " Option.
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Hi, There are some examples with ModelSim, they are some how big designs .. if you want them i can upload them.
  18. W

    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Hi, What i know is that you can use TCL or DO files ; and i think that PSL files stands for Property Specific Language. PSL is designed to be used by both formal (mathematical proof) and dynamic (simulation based) methods of checking.
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    What is the use of generate statement here ?

    Re: Generate Statement Hi, The Generate Statement in Verilog differs from the for loop, that it adds a specific parts of verilog code to the module depending on the conditions, which helps that the code in a module ---> Instance functionality , can be variable according to the parameter passed...
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    Looking for documents about System Verilog DPI

    dpi verilog Hi, Here is a website from Google : https://www.project-veripage.com/dpi_tutorial_1.php and you can use the SystemVerilog LRM, it contains a section about DPI.

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