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Here is the code
architecture Behavioral of fsk is
signal i : integer := 0;
signal k : integer := 0;
signal b : std_logic := '0';
signal o_dummy : integer := 0;
signal temp : std_logic := '1';
signal j : integer range 0 to 249;
signal c : integer := 0;
signal c1 : integer := 0;
signal c2 ...
Hello...I am very new to VHDL.. I have generated sine wave in VHDL.. But the problem is that some samples are missing in the output and so the wave is distorting... In PSK,FSK programs the same problem is occurring.. What should i do?? I tried matching the frequency but still the result is...