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  1. C

    Sine wave- missing samples

    Does anyone have idea to solve this??? This problem is repeating if i combine waveforms like pulse,ramp,square in a single output.
  2. C

    Sine wave- missing samples

    Yes.. The output is from c1 for 2001 cycles.. But the count for 2001th cycle is 0. And the next cycle is starting from 1.
  3. C

    Sine wave- missing samples

    Yes i placed them as you said, but still the result is same. After many cycles the distortion in the signal is making it look like a PSK signal
  4. C

    Sine wave- missing samples

    Yes.. The sample values are not starting at the same time the counter is starting.. But I am assigning c1 and c2 every clock cycle right?? Where am I wrong??
  5. C

    Sine wave- missing samples

    Here is the code architecture Behavioral of fsk is signal i : integer := 0; signal k : integer := 0; signal b : std_logic := '0'; signal o_dummy : integer := 0; signal temp : std_logic := '1'; signal j : integer range 0 to 249; signal c : integer := 0; signal c1 : integer := 0; signal c2 ...
  6. C

    Sine wave- missing samples

    Hello...I am very new to VHDL.. I have generated sine wave in VHDL.. But the problem is that some samples are missing in the output and so the wave is distorting... In PSK,FSK programs the same problem is occurring.. What should i do?? I tried matching the frequency but still the result is...

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