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  1. R

    Can I place all PMOSs in one Nwell?

    Re: PMOS in Ntub? sharing Ntub does not have good electrical characteristics.
  2. R

    Why this topology is called a comparator?

    Re: comparator the first stage is the resistively loaded comon source amplifier stage.
  3. R

    drc error in cadence--hot nwell

    hot nwell hai, i am getting DRC error as HOT NWELL while running drc for any circuit in cadence VIRTUOSO layout editor. how could i rectify this.
  4. R

    preamp used in comparators

    reduce kickback comparator in comparators(latched comparators) very low gain pre-amplifiers are used . what is the use of this pre-amp.
  5. R

    problem running LVS in Cadence

    i could not rectify the problem. how could i rectify it
  6. R

    Help for Magma also........

    Magma material is found in this link
  7. R

    dynamic and static power dissipation

    refer to "Digital integrated circuits" by Jan Rabey. Dynamic power dissipation=F*C*Vdd*Vdd F=Frequency C-capacitance Vdd-power supply
  8. R

    analog layout materials for beginners

    hai, i have started drawing layout using cadence for Comparator.tell me where to refer for this. possible send me some books or some materials for this.
  9. R

    Help for Magma also........

    you could find that in the doc tab of magma and user guides will be available in that.
  10. R

    Looking for bandgap reference books

    Re: bangap reference books for analog ckts refer to cmos analog ckt design by philip allen
  11. R

    Looking for bandgap reference books

    bangap reference books for analog layout refer to art of analog layout by alan hastings
  12. R

    gain of dynamic latch comparator

    how the resolution of the this latch can be increased. whether resolution is depending upon size of latches alone.....please help.
  13. R

    gain of dynamic latch comparator

    i am not able to increase the gain of the pre-amplifier stage beyond 2V/V. is this gain sufficient for the design. gain is low because the load for M1 and M2 transisters are in trode region(according to the design). how can I design the dynamic latch.
  14. R

    problem running LVS in Cadence

    disk quota exceeded cadence I get problem called "unable to build VDB file" while running LVS in cadence virtuoso. what does it mean and how can i oversome this.

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