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  1. sachinagg77

    Programmable Gain Amplifier

    switched capacitor programmable gain amplifier Dear All I am presently designing a switched capacitor based PGA. The gain is set using a variable feedback capacitor. Many capacitors are connected between the op-amp input and the output. Suitable feedback capacitance is selected using switches...
  2. sachinagg77

    Noise Analysis of Switched Capacitor PGA

    noise analysis switched-capacitor I designed a switched capacitor PGA for gain settings of 0dB to 12dB. To check the thermal/flicker noise contribution of this circuit, I used .NOISE analysis (spectre). The circuit was kept in closed loop. I would like to request for feedback on the...
  3. sachinagg77

    Low Power Pipeline ADC

    low power pipeline adc Dear Friends I am looking for ideas on designing a low power pipeline ADC. I am considering sharing op-amps between consecutive stages. Any feedback or suggestions on this will be highly appreciated. Regards Sachin
  4. sachinagg77

    Switched Capacitor Sample and Hold Circuit: KT/C Noise

    kt/c noise Dear Friends I would be grateful if someone could explain the KT/C noise (input referred) contribution of Sampling Capacitor (CS) and feedback capacitor (CF) for the standard two capacitor S/H implementation (not the flip around architecture). Regards Sachin
  5. sachinagg77

    Impact of load capacitor on the slew rate of a standard two stage op-amp

    Hello Can someone please explain the impact of load capacitor on the Slew Rate of a standard two stage op-amp? In addition, can the use of cascoded miller compensation improve the slewrate performance of an op-amp? I will appreciate if someone can point out the method to derive the slewrate...
  6. sachinagg77

    Weird THD results of a SH circuit

    Dear Friends I designed a SH circuit as first stage for my pipeline ADC. I use Cadence Analog Design environment and spectre for simulations. I performed a DFT analysis on data obtained by transient analysis (coherant sampling, strobeperiod option used). The plot looks fine. I also included...
  7. sachinagg77

    Question about performing the FFT on the ADC output

    I am designing a 10bit ADC. I would be thankful if someone could answer the following query: While performing the FFT on the ADC output, is it necessary to select the number of sample =2^N where N is more than the ADC resolution? In other words, is it fine to select N<10 (=7) for a 10 bit ADC...
  8. sachinagg77

    Analog Design Environment Cadence: Plot options

    cadence plot I use the Cadence environment for simulating my analog circuits. Most of the time, I am able to see the simulation results at any point of time during the simulation. Sometimes, the results are not plotted until the complete simulation is finished. I don't know what causes this...
  9. sachinagg77

    Standby Mode: Analog Circuit

    check circuit floating node What means should be adopted to identify all possible cause of leakage during the standby mode for an analog circuit? What should be done to ensure that there is no leakage current during the standby mode? With Regards Sachin
  10. sachinagg77

    Pipeline ADC: Reference Noise

    I am presently designing a pipeline ADC. I am trying to calculate the total input referred noise for the circuit. Can anyone suggest how to get the input referred value for the noise contributed by the reference circuit (used in MDAC)? Thank You Sachin Aggarwal
  11. sachinagg77

    Reference Buffer: For high Speed pipeline ADC

    dac reference buffer For my pipeline ADC [110MHz] design, I need to design an internal reference buffer circuit, to provide reference to my MDAC circuit. I would be grateful if some one could provide some referenced for voltage buffer design [for high speed Switched Capacitor Circuit]. Thank...
  12. sachinagg77

    Closed Loop Impedance vs Frequency: OP-AMP

    I would appreciate if someone could suggest the simulation set up to get the "Closed Loop Impedance vs Frequency" plot for a buffer [amplifier in unity feedback configuration].
  13. sachinagg77

    Clock Duty Cycle Correction Circuit

    duty cycle correction circuit I intend to design a "Clock Duty Cycle Correction Circuit" that can handle input clocks with duty cycle ranging from 20% to 80% and output a clock with 50% duty cycle [with a tolerance of 1%]. Another important requirement for the circuit is LOW JITTER performance...
  14. sachinagg77

    NBTI degradation & its impact for analog circuit reliabi

    NBTI: Request for paper I would be grateful if someone could provide information about the NBTI related effects on Analog Circuits like comparators and op-amps. In addition, if available, please provide me with the following technical paper. NBTI degradation and its impact for analog circuit...
  15. sachinagg77

    SH configuration for pipeline ADC

    sh configuration I would like to clarify a doubt about the single-capacitor flip-around Sample & Hold configuration for pipeline ADC. I am aware of the relative advantges of this configuration as compared to the other configurations [like two capacitor configuration etc] but I find that this...

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