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The schemetic is attached below.
The aim is as follows:for a given period clock signal with any duty cycle,the Integrator will translate it into DC(with little ripple) voltage proportional to the period.(I'm not sure is it the so called frequency-to-voltage converter).
In a patent I encountered a block so called "clock phase mixer",
which can average the rising edge and falling edge of two clocks.
(see the waveform below,note the red reference line).
How we relize it with circuit?
According to many Data Sheets(say AD9245,ADS5413),many high speed,high resolution ADCs employ a clock duty cycle stabilizer.
I just wander how clock duty cycle affects the performance of ADCs.
I also find that most ADCs employ such module are Pipeline ADCs.
Then what about other Architectures...
My graduation thesis is DCS(duty cycle stabilizer) or DLL in highspeed & highresolution ADCs.
Is there anybody have some papers on this topic?
Would you please upload here or mail to:email@example.com.
Thank you in advance!:D