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  1. asic_ant

    The relationship between the pole freq and settling time of an OPA

    who has the matlab code to determine the relationship between the pole freq and settling time of an OPA, or any book about that? thank you!!!!!!
  2. asic_ant

    Hspice error:internal timestep too small in transient...

    interal timestep too small I often encounter such error. How to deal with it usually?
  3. asic_ant

    Looking for papers about clock in pipeline ADC

    please, anyone know about the clk in pipelined adc? or any paper or book about it ?
  4. asic_ant

    Question about an OP-amp model...

    It is an OP model from ahdlLib in Cadence. Why there is a "Vref" pin? And how to use it?
  5. asic_ant

    What's the operating Points regions stand for? (in Spectre)

    When I use HSPICE,it direct indicate the "saturation","cut off","linear". But when come to spectre it is region 1,2,3 Then what are they stand for respectively?
  6. asic_ant

    Need help for an integrator design!

    The schemetic is attached below. The aim is as follows:for a given period clock signal with any duty cycle,the Integrator will translate it into DC(with little ripple) voltage proportional to the period.(I'm not sure is it the so called frequency-to-voltage converter). Besides,the clock...
  7. asic_ant

    How to carry out the zero/ploe analysis?

    In Allen's book he used a lot, but I just can't understand...
  8. asic_ant

    What is a "clock pahse mixer"?

    In a patent I encountered a block so called "clock phase mixer", which can average the rising edge and falling edge of two clocks. (see the waveform below,note the red reference line). How we relize it with circuit?
  9. asic_ant

    Confused by a circuit.

    It is supposed to be a dutycycle stabilizer related schemetic. Any suggesting??? Thanks a lot.
  10. asic_ant

    Which structure is better?

    This will be a clock generator in a pepelined A/DC. For A,the S&H can achieve the better time margin from DLL. For B,jitters caused by DLL will affect the S&H. Any ideas?
  11. asic_ant

    What is a 2-Phase Non-Overlapping Clock?

    two phase non overlapping clock For pipeline ADCs...
  12. asic_ant

    Can DLL maintain a 50% duty cycle inherently?

    phase blending dll Or we have to employ extra module to ensure 50% duty cycle?
  13. asic_ant

    How to change the wire nets' color in Cadence?

    cadence xhange colours net Any ideas? Thanks in advance.
  14. asic_ant

    How duty cycle affects the performance of ADCs?

    According to many Data Sheets(say AD9245,ADS5413),many high speed,high resolution ADCs employ a clock duty cycle stabilizer. I just wander how clock duty cycle affects the performance of ADCs. I also find that most ADCs employ such module are Pipeline ADCs. Then what about other Architectures...
  15. asic_ant

    Looking for books on data converter

    Any books on Data Converter recommended? Are they available in this forum? Thanks in advance!
  16. asic_ant

    How we get a "high" logic voltage?

    Can I just connect it to vdd through a resistor? In a schemetic I found it adopt a long channel pmos transistor with its gate connected to gnd throough a resistor. Why we do this?
  17. asic_ant

    What is the "false lock" in DLL???

    It seems both the output clock in the correct case and the false lock case have the same frequency and the aligned pahse? So where on the earth does the "false" happens?
  18. asic_ant

    Help with my graduation design

    My graduation thesis is DCS(duty cycle stabilizer) or DLL in highspeed & highresolution ADCs. Is there anybody have some papers on this topic? Would you please upload here or mail to:shadow1983@56.com. Thank you in advance!:D
  19. asic_ant

    What are the tools for analog IC designer?

    A green hand : ) To be a competent analog IC designer,what tools shall I grasp!
  20. asic_ant

    SOS! Hspice simulate failure

    **error** no convergence in operating point *** *** hspice diagnostic *** nonconvergent voltage failures= 0 nonconvergent element current failures= 1 in such case,how shall I tackle?

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