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    Job advertisements in Malaysia

    Jobs.... >> Jobs advertisement. www.jobstreet.com.my
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    HDL turbo writer installer-The best HDL text editor?

    hdl turbo writer I'm looking for HDL turbo writer. In fact, i did contact SAROS Inc to get the installer. Unfortunately, they no longer product this software for many years ago. Do anyone here can share me the installer/evaluation installer? What do you guys think about the best HDL text...
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    HDL turbo writer download

    hdl turbo writer Anyone can share HDL turbo writer with me? What is the advantage? Izzit freeware? How to get it?
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    Xilinx Development kit wanted...

    *Private Msg...
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    VHDL jobs in Bangladesh...

    *Private Msg...
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    Share ...FPGA training course material from Xilinx/ALTERA

    Share material wif me..
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    A website with Singapore FPGA Jobs

    Singapore Jobs... www.jobstreet.com.sg -> Singapore FPGA jobs...Search search search..
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    Xilinx Training Material...

    xilinx training material download Do anybody has the FTP site from Xilinx to download the Xilinx Training Material? Please share with us how to link to FTP site and download the valuable training course material. Thanks.
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    TCL, PERL and Kornshell programming...

    I hope to learn scripting in order to automate the FPGA design... Which one should i go for? What is the advantages for each one? Thanks.
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    What are the factors that increase Clock Path Skew?

    Clock Path skew is caused by placement between source (FF) and destination(FF). Beside placement bet. FFs, is there any factor will increase clock path skew?
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    IMPORTANT VERILOG CODING PROBLEM

    Case A: always @(ctrl or dataIn0 or dataIn1) dataOut <= (ctrl) ? dataIn1 : dataIn0; Case B: always @(ctrl or dataIn0 or dataIn1) dataOut = (ctrl) ? dataIn1 : dataIn0; Which case is correct? WHY?
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    Is post P&R simulation useful in FPGA design?

    Post P&R simulation Is post P&R simulation useful in FPGA design? Do you think it just wasting the times for doing P&R???!!
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    systemVerilog verification

    I'm writing my code in verilog 2001. Can i use systemVerilog in test bench coding to verify my RTL code in verilog 2001? Thanks.
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    Why the synthesis tool does the pruning register?

    I always see the message in synthesis tool : Pruning register. Why the synthesis tool doing the pruning register? will it change the functionality of circuitry? Thanks.
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    Question about Verilog RTL syntax

    Izzit any different between below case? Case 1: always @(posedge clk_i) begin game_a_0 <= game_a_i; game_b_1 <= game_b_i; end Case 2: always @(posedge clk_i) game_a_0 <= game_a_i; always @(posedge clk_i) game_b_1 <= game_b_i; Will case 2 be better for synthesis tools to...
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    Verilog Syntax: difference between 5'h01 and 'h01

    Is that any different between 5'h01 and 'h01? Does it cause any error if writing as 'h01?? Regards, Choon Lin
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    Design Verfication Solutions

    How to generate a good verification testbench? How can be defined as good verification testbench??!!
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    Any Simple method to test Function in Verilog

    Test the function in Verilog can be boring if u try to run simulation and see the output. Do you think any method can be faster to rest function whether correct or not>
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    Verilog Syntax %s and %0s

    %s and %0s + verilog what is different between %s and %0s?
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    Wanted: SystemVerilog Ebook

    Hi, Can anyone share systemVerilog Ebook? Bonus Point will be given if anyone share the ebook regarding to systemVerilog and not Verilog! Thanks.

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