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    Synopsys Backend tool with AMS 0.35 um CMOS -> Cadence files ?

    Hello, I'm currently designing a mixed-signal IC, and after some unsuccessful try-outs with Tanner Ledit (SPR), I'm considering switching to the Synopsys Backend tools, for generating the digital lay-out. The technology I am using is AMS 0.35 um CMOS. The foundry provides the necessary files...
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    Tanner EDA: digital design flow (from VERILOG to layout) ?

    Hello, I am using the Tanner EDA tools with the AMS 0.35 PDK, and I was wondering how I could synthesize VERILOG code into a layout in Tanner L EDIT (or an EDIF file that can be imported using the standard place and route tool of Tanner). The Tanner website (L-Edit - General - How does a...
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    Convert VERILOGA to EDIF, and import in Tanner L EDIT

    Hello, I am an analog IC designer, using Tanner EDA, and I need to design a mixed signal chip. I am considering designing the digital part of this chip in VERILOGA. According to the Tanner manual, the layout place and Route tool is able to import EDIF files. My question therefore is what...

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