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  1. O

    Please HELP! error in AMBA protocol V2.0? AHB read data mux controlled by decoder?

    I think the arbiter is not just combinational logic. Hope more people can reply to this question.
  2. O

    Please HELP! error in AMBA protocol V2.0? AHB read data mux controlled by decoder?

    i read the protocol 3 times and I think i understand it. Based on the protocol, the address decoder is combinational logic. its inputs are just the address from the master, so its outputs are in the same cycle with the address cycle. But ahb's data cycle is one cycle after the addr cycle. So in...
  3. O

    SRAM read/write access time and operating frequency

    Hi all, Can anyone explain the relationship between the operating frequency and the read/write access time in sram. Best, - - - Updated - - - find some answer from a manual and share the answer with guys here. but still have some question about this. Why access time can be larger/equal to...
  4. O

    write operation of 6T sram

    Hi all, I have a question about write operation of 6T sram I know for sram read: phy2 : Precharge both bitlines high phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell for sram write, my question is that during phy2, does the bitline and bitline_bar need to...
  5. O

    APB clock and AHB clock

    hello all, can anyone explain the relationship between the clock of AHB and APB. Hope someone can reply....
  6. O

    confuse about AHB deadlock

    Hi ALL, I have a question about when the AHB can be deadlocked. I get this question in the AMBA protocol pdf from ARM but it seems that it's not clear enough for me. And I found something in the ARM information Center, which says: " Does a master need to issue non-LOCKed accesses when...
  7. O

    How to fix setup time violation after synthesis?

    is there any step after synthesis can fix this problem? can i guide the P&R to have some usefull clock skew for that?
  8. O

    Difference between timing constraint scripts used in dc,pt in different stages

    hello, what is the difference in timing constraint for dc and pt, and P&R and post-layout STA. thanks in advance
  9. O

    will non_full_case infer priority decode circuit?

    would you plz summarize the situations when case state will refer to priority encoder? I think I mess something up here. it seems that without synopsis parallel_case directive, case and casez will always refer to priority encoder no matter whether the case items are parallel or not. but if we...
  10. O

    will non_full_case infer priority decode circuit?

    always @ (a or b or c or select2) begin r = c; case (select2) 2'b00: r = a; 2'b01: r = b; endcase end in an article, it says this will infer a priority, but I don't think so. can anyone correct me if i am wrong. this is just a non-full_case case statement, why it will infer priority. priority...
  11. O

    Ping pong effect in RTL compilation

    I still can not understand this pingpong effect. would anyone can post an example here? and more, why it create long layout-dependent timing path? This forum is sooooo good, learn a lot here. will recommend my friends to join this forum.:grin::grin:
  12. O

    [SOLVED] Synchronous clock division

    hello, can you explain more about clock enable, what does it mean and why it's better?
  13. O

    do synthesis tool distinguish which is clk which is rest of a ff?

    you said "assign two clock buffers". i don't quit understand this. do you mean if synthesis tool treat it as clk, then it will buffer it by default. I am wondering this because i read some articles and they says don't use data to connect to the clk of fflop because the synthesis tool treat them...
  14. O

    do synthesis tool distinguish which is clk which is rest of a ff?

    module which_clock (x,y,q,d); input x,y,d; output q; reg q; always @ (posedge x or posedge y) if (x) q <= 1'b0; else q <= d; endmodule In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or...
  15. O

    latch in verilog should use nonblocking assignment ?

    hello all, i read a article about blocking and nonblocking, it says that latch should be implemented using nonblocking assignment. but i don't know what's the reason for this. can anyone explains this a bit more. thanks in advance.
  16. O

    positive edge trigger rtl

    sorry for the confusion, how about counting the edges? is that what you mean in #13. you said "counting edge can work with a gray code counter....", using gray code mean every moment at most one bit is changing. no matter whether that toggling bit passed to the new clk domain or not, it will...
  17. O

    positive edge trigger rtl

    Thanks.I agree with you that the timing between the signal and the clk should be specified. I don't understand your comment can you recommend some articles about this(preferred :-D) or give more details. my question is "do you mean using a gray counter in the source clock domain and then send...
  18. O

    in verilog, combine edge trigger & blocking assignment

    I am quite new with verilog, please share any idea you have. in many articles, they only said that edge driven logic, logic in always @(posedge XXX), will be synthesis as flipflop. Should we say that logic using non-blocking assignment in the @(posedge XXX) procedural block will be synthesized...
  19. O

    positive edge trigger rtl

    Do you mean this? My code can only detect the pulses that are one clock away from each other. the signal drive the first flip flop,FF1, which toggles its output when signal has risedge. and then the output of the FF1 works as input of FF2, FF2 works as input of FF3, output= D_{ff2} xor...
  20. O

    how to use best case, worst case, typical case of a technology

    so for safe, i use the xxxwc.db as target library and then include both the xxxwc.db and xxxbc.db in the link_library, and then in the dc script, I use set_operating_conditions -min BESTCASE -max WORSTCASE? if so, dc will check timing using either bestcase or worstcase, right? but finally, dc...

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