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  1. K

    problem with simulation in Modelsim in UNIX environment

    when i simulate the ROM module the following error is coming. pls help me regarding this Exited with exit code 12. this refers to problem during load or elobaration vsim rom.v # ** Error: (vsim-19) Failed to access library 'rom' at "rom". # No such file or directory. (errno = ENOENT) #...
  2. K

    BIP(Bit Interleaved Parity)- VHDL Code

    bit interleaved parity-8 Hello all, I want to implement BIP-8 for SONET/SDH( Bit Interleaved Parity) for FPGA. Anybody is having VHDL code, please inform. with regards, rajendra

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