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  1. V

    VHDL Basic Input and Output Text File

    Thank you so much for helping me. This really helped. I think I am able to finish my project. Thanks again.
  2. V

    VHDL Basic Input and Output Text File

    You are correct. I apologize, but I am having a bit of trouble implementing your suggestion. The code is a bit different from before, but it seems to be the same principle. You will notice that there is no while loop anymore, instead there is a for loop because I am using a modified example from...
  3. V

    VHDL Basic Input and Output Text File

    Thanks for the reply. I am currently having an issue converting the code to string representation. Currently I have: variable string1 : string(1 to 80) := (others => ' '); begin while not endfile(myfile) loop readline(myfile,inline); --end_of_line is EOLN boolean flag...
  4. V

    VHDL Basic Input and Output Text File

    Nice, that worked perfectly! Thank you so much once again. You have really helped me a lot. I really appreciate it.
  5. V

    VHDL IEEE Package for Real Number Arithmetic

    Thank you very much that was very helpful. But, what do you mean by "On the other hand fixed point is just integer arithmatic." Do you mean to say that I don't need a floating point package to calculate what I am trying to accomplish? I am trying to keep it as synthesizable as possible (within...
  6. V

    VHDL Basic Input and Output Text File

    Thanks for the reply. I used the code you have provided and that fixed the ordering issue. However, the output still has an extra d. It outputs "abcdd" instead of just "abcd". Is it possible to fix this? while not endfile(myfile) loop readline(myfile,inline); --end_of_line is...
  7. V

    VHDL IEEE Package for Real Number Arithmetic

    I apologize for making another thread so soon, but I could use some help on another topic. From my understanding in order to represent real numbers you have to use floating point or fixed point numbers and most implementations use the IEEE 754 standard. So, my question are as follows: 1. What...
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    VHDL Basic Input and Output Text File

    Thanks for the reply, but I am having trouble implementing what you suggested in step 1. There are two loops. a while not and a while loop inside of the while not loop. I see a read call in both of these loops. However, I do not see a read call before the while not loop starts. There is just a...
  9. V

    VHDL Basic Input and Output Text File

    Hello, I am trying to read a single line from a text file and then output it to another text file. Here is my current code: library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use Ieee.std_logic_unsigned.all; use std.textio.all; entity tb_project is end...
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    VHDL optimal division

    Thanks so much. That really cleared things up. The only thing I am still confused about is the initial shift. How would I compare the numbers bit by bit to know how many times to shift it? Also, I am interested in the fraction portion for the remainder. The answer should be 18.25. How would I...
  11. V

    VHDL optimal division

    I am okay with binary, it's just I had a little trouble understanding the steps involved: Can you please elaborate on these steps? For example, 73/4 or 1001001 / 100. How would the answer be generated as well as the remainder? Thanks again. Alright, thanks for the information. I will make it...
  12. V

    VHDL optimal division

    Thanks for the reply. This was an assignment. I forgot to mention that. The asynchronous reset was a specification. I will put it in a separate process. However, it also said to use (10 bit) unsigned quantities. In the past were were mostly using vectors so I thought we were suppose to use...
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    VHDL optimal division

    Hey there, I am having problems modifying my basic division code to an optimal solution using state machines. The simple state machine design is basically to subtract at each clock cycle. I have an example of it below: library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all...
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    FPGA Project Assistance: FPGA and Component Selection Assistance

    FPGA Project Assistance: FPGA and Component Selection Hello, I am a student taking a VHDL course and I am looking into FPGA's that could potentially be used with my desired project. The project I am looking into utilizes a touch screen (2-4" in size). I have searched this site and a few others...

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