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  1. R

    What's the cutoff frequency of TSMC 65nm process?

    Hi, I haven't used the TSMC 65nm process, I'm wondering what's the number of its fT (cutoff frequency)? Thanks, Ruri
  2. R

    inverter delay in Simulink

    Hi all, I want to add some delay to the inverter in Simulink, not integer cycle, for example, 0.3 Tcycle, or 0.2 Tcycle. It seems no way to do that in Simulink? any hint? Thanks, Ruri
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    Interesting: Will SAW Help Improving the Chain NF?

    Hi, all, Let's consider a 50 ohm to 200 ohm impedance transformation SAW filter, and it has the insertion loss of 1dB. If it is inserted between a 50 ohm antenna and a 200 ohm LNA, will it help with the chain noise figure, or the noise figure of SAW+LNA will be better than LNA alone (refer to...
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    How to simulate the group delay of a switched cap. filter?

    simulate pss delay Dear all, I want to simulate the group delay of a switched capacitor filter, however, after running the PSS+PAC simulation, I could not use the "special function" in the calculator. So, is there any other method to calculate the group delay? Thanks in advance, Ruri
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    Low noise amplifier design with -10dB gain?

    Hi, gentlemen, Does anyone here has the experience of designing LNAs with negative gain like -10 ~ -20dB and keeping the input impedance matched at the same time? OR do you have any suggestions or references? Thanks in advance. Ruri
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    How to measure the DC noise?

    Hi, all, How to measure the DC noise performance, say the LDO, BG output noise? what equipment can be employed? Thank you very much, Ruri
  7. R

    Phase Noise Simulation of Ring Osc. with spectreRF

    phasenoise simulation Hi, all, How to get the right phase noise curve in spectreRF?? I got the positive one for the close-in, thought it must be wrong. Thanks in advance, Ruri
  8. R

    200MHz Power Amplifier

    Hi, all, Does any one here have the experience of designing the 200MHz inductor-less power amplifier to drive 50 ohm antenna, with output power around 0dBm? Thanks in advance, Ruri
  9. R

    50ohm driver/buffer for measurement

    driver 50ohm Hi, all, Does anyone here have the experience of designing the on-chip 50ohm driver/buffer for cable connection with testing equipment? The requirement on the driver/buffer are: wide bandwidth, high linearity and driving capability. Thank you in advance, Ruri
  10. R

    THD simulation in Cadence Spectre

    cadence thd Hi, guys, How to simulate the total harmonic distortion (THD) in Cadence Spectre simulator? Many thanks, Ruri
  11. R

    compact capacitor layout?

    compact capacitor antennas Hi, what's the most compact on-chip capacitor you've ever built? any layout technique? take 5M1P process as an example. Thanks, Ruri
  12. R

    Looking for resources about RF VGA design

    Hi, all, does any one here have the experience on the RF VGA design? or have any material on the topic. For example, the gain range:42dB, step: 3dB? Thanks, Ruri
  13. R

    Why do I get unsymmetric Mag E plot in HFSS?

    Hi, I simulated an totally symmetric inductor in HFSS, but when I check the E field, I found that the plot is totally un-symmetric, I even can not see another port !! (I changed the phase and do the annimation, but still found the unsymmetry). Attached please find the Mag_E plot, thanks. Ruri
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    What's wrong with my current distribution in HFSS?

    how to get current distribution in hfss Hi, all, I'm using HFSS to simulate an on-chip inductor, but whatever setting I used, still get bad results comparing with the measured data: the inductance is about 0.1nH larger, and the quality factor is about 6 less. Someone told me that the current...
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    ASITIC problems: round-off error, KCL violation, s-parameter

    Help: ASITIC Problems Hi, 1. While using ASITIC to simulate inductors, when I turned on the eddy option, I kept getting the "round-off error" messages, why and how to solve this problem? 2. Why do I get the warning messages of "KCL violation"? is this warning important? 3. While modeling...
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    How to import S2P file into Cadence SpectreRF?

    cadence s2p Hi, I'm using ADS Momentum to calculate the S-parameter of the inductor, and I have the problem of importing the s2p file into SpectreRF. I found some references suggest to use the 'sptr' commond under spectre to translate the s2p file into the s-para file that spectreRF...
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    Help: on chip inductor layout?

    inductor layout Hi, Is anyone here have any experience on on-chip layout? Please help me out ... 1. Does the inductor layout need substrate contact which ties to ground? Why and Why not? 2. Does the inductor need n-well under it? 3. Does the PGS (Patternedound Shield) need to be tied to...
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    Discussion on ASITIC and On-chip Transformer Design

    Hi, 1. I'm now using the ASITIC to design a transformer, however, I found it's difficult to dump the transformer's S-Paramter (two port s parameter, the target transformer structure is just like the one indicated in the attached pix). 2. how to add ground to some of the inductor's terminals...
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    Some Parameters Needed for ASITIC Simulation

    Hi, I'm now using TSMC 0.25um RF/MS process to design inductors, the simulating tool is ASITIC. Unfortunately, the foundry would not provide the parameters such as substrate thickness (T), substrate resitivity(ρsub), and the oxidation layer resitivity(ρoxi), etc. In addition, the permeability...
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    A question on one of Lee's paper on LNA

    Hi, I have a question on one of the most often cited papers of Thomas H. Lee's: "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier" (IEEE JSSC, Vol.32, No.5, 1997) Where does the denominator (1+ωT*Ls/Rs)² come from in the equation (12)?? Isn't that the channel resistance noise (id) itself is located...

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