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Let's consider a 50 ohm to 200 ohm impedance transformation SAW filter, and it has the insertion loss of 1dB. If it is inserted between a 50 ohm antenna and a 200 ohm LNA, will it help with the chain noise figure, or the noise figure of SAW+LNA will be better than LNA alone (refer to...
simulate pss delay
I want to simulate the group delay of a switched capacitor filter, however, after running the PSS+PAC simulation, I could not use the "special function" in the calculator. So, is there any other method to calculate the group delay?
Thanks in advance,
Does anyone here has the experience of designing LNAs with negative gain like -10 ~ -20dB and keeping the input impedance matched at the same time?
OR do you have any suggestions or references?
Thanks in advance.
Does anyone here have the experience of designing the on-chip 50ohm driver/buffer for cable connection with testing equipment? The requirement on the driver/buffer are: wide bandwidth, high linearity and driving capability.
Thank you in advance,
I simulated an totally symmetric inductor in HFSS, but when I check the E field, I found that the plot is totally un-symmetric, I even can not see another port
!! (I changed the phase and do the annimation, but still found the unsymmetry).
Attached please find the Mag_E plot, thanks.
how to get current distribution in hfss
I'm using HFSS to simulate an on-chip inductor, but whatever setting I used, still get bad results comparing with the measured data: the inductance is about 0.1nH larger, and the quality factor is about 6 less.
Someone told me that the current...
Help: ASITIC Problems
1. While using ASITIC to simulate inductors, when I turned on the eddy option, I kept getting the "round-off error" messages, why and how to solve this problem?
2. Why do I get the warning messages of "KCL violation"? is this warning important?
3. While modeling...
I'm using ADS Momentum to calculate the S-parameter of the inductor, and I have the problem of importing the s2p file into SpectreRF.
I found some references suggest to use the 'sptr' commond under spectre to translate the s2p file into the s-para file that spectreRF...
Is anyone here have any experience on on-chip layout? Please help me out ...
1. Does the inductor layout need substrate contact which ties to ground? Why and Why not?
2. Does the inductor need n-well under it?
3. Does the PGS (Patternedound Shield) need to be tied to...
1. I'm now using the ASITIC to design a transformer, however, I found it's difficult to dump the transformer's S-Paramter (two port s parameter, the target transformer structure is just like the one indicated in the attached pix).
2. how to add ground to some of the inductor's terminals...
I'm now using TSMC 0.25um RF/MS process to design inductors, the simulating tool is ASITIC. Unfortunately, the foundry would not provide the parameters such as substrate thickness (T), substrate resitivity(ρsub), and the oxidation layer resitivity(ρoxi), etc.
In addition, the permeability...
I have a question on one of the most often cited papers of Thomas H. Lee's: "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier" (IEEE JSSC, Vol.32, No.5, 1997)
Where does the denominator (1+ωT*Ls/Rs)² come from in the equation (12)?? Isn't that the channel resistance noise (id) itself is located...