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    How to comment out part of a DEF file?

    For some debugging purpose, I need to comment out SPECIALNET sections or part of SPECIALNET sections. The tool is Cadence. However, I notice there are tens of thousands of lines in my DEF for one special net. What is the best way to comment out a range of lines in DEF file?
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    What is the relationship between preroute extraction and congestion calculation?

    To my understanding preroute extraction is to simply calculate r_per_um and c_per_um on each grid of the floorplan, before routing. Congestion calculation happens after routing, to reflect congestion_H and congestion_V. Is my understanding correct? Does congestion calculation requite any...
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    What is the definition of macro in Cadence?

    I am confused about the definition of macro, together with some other concepts (i.e inst and hinst) To my understanding, macro corresponds to std cells with dimension and coordinate information. But Cadence seems to merge "macro", "inst" and "hinst" together. It seems to me, an "inst" and...
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    What is the ring concept for placement blockage?

    Thank you so much for your response. However, I still have some trouble with visualizing it in my mind, because I don't understand how it works when both "inner_ring_by side" and "outer_ring_by _side" are specified, like this: create_place_blockage -hinst something -inner_ring_by_side {10 10...
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    What is the ring concept for placement blockage?

    I came across a Cadence command "create_place_blockage" for Innovus tools, which is like this: create_place_blockage -hinst DT_INST/RESS_CONV_INST -inner_ring_by_side {10 10 10 10} -outer_ring_by_side {5 5 5 5} But I did not find the documentation of this command, so I am trying to understand...
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    How to identify driver and loads of a net from SPEF file

    Thank you for the instruction. - - - Updated - - - Thank you so much for the clarification. Yes, the direction definition in SPEF confused me a lot.
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    How to identify driver and loads of a net from SPEF file

    Thank you so much for your instruction. I am not very familiar with concepts like ports and internal pins, but a driver can usually have one drive and one or more loads, right? In order to tell which node is drive and which are loads, were you looking at the CONN section only? Here is another...
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    How to identify driver and loads of a net from SPEF file

    Thank you for your response. I read the wiki page, but still wondering how to apply the synatx to my examples. That the first net as example: *CONN *P *1803 O *I *4393:Y O *L 0.0000 *D TGAMUX2XC #### I guess node *1803 is a port output. #### I guess node...
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    How to identify driver and loads of a net from SPEF file

    I need to identify driver and loads of a particular net. But I have some trouble understanding the syntax of SPEF file. The following is an example with 2 nets: *CONN *P *1803 O *I *4393:Y O *L 0.0000 *D TGAMUX2XC *CAP 1 *3608:2 0.000184248 2 *3608:3 0.0002920536 3 *3608:4 0.0002920536 4...
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    What is the physical meaning of a layer being "TRIM"?

    I only know that, in LEF files, there are definitions of ROUTING layers and CUT layers. Now we need to identify if a particular layer is "TRIM" or not, based on the info in LEF file. In other words, I am trying to write a parser for LEF files, and there should be a "is_layer_trim" attribute for...
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    How are LEF, DEF, QRC Techfile and Capacitance table file related to each other?

    I am new to this field and I don't have a good understanding of the flow. Could anybody help me to understand LEF, DEF, QRC Techfile and Capacitance table files? My current understanding is that: (1) LEF has "cell level" information, while DEF has "floorplan level" information. In this sense...
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    How to set a NET in DEF file as FIXED?

    My boss wants to prevent routing tools from modifying some particular nets. So he asked to "mark those nets to something like i.e. +FIXED, so it won't be changed by the router. " Could anyone tell me if it works? If so, what exactly should I do to the DEF file? An example will be really...
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    [SOLVED] What are Tracks and how are they generated?

    I was asked about the tracks and how to generate them. So I did a quick search online. Now my basic understanding is that, tracks are not any physical wires or cells. They are paths in which the routing tool can put wires. I am not sure exactly when tracks are generated. My guess is: (1)...
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    What caused errors when compiling U-Boot?

    Thank you very much. Do you mean this problem might be caused by my operations for hardware part with XPS? I remember I added RS232_UART_1 to the AXI bus. How can I specify the type of IP to be used? - - - Updated - - - This is what I saw from Xilinx Platform Studio: - - - Updated - - -...
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    What caused errors when compiling U-Boot?

    I followed the instructions in https://xilinx.wikidot.com/mb-uboot to compile U-boot linux-host> export BUILD_DIR=$PWD/build linux-host> make microblaze-generic_config linux-host> make And I got the following information on the terminal: CHK include/config.h UPD...
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    Questions about porting Linux OS on Microblaze with Virtex6 board

    Thank you sir for your reply. I follow this manual to do the experiment https://www.scribd.com/doc/63732567/Microblaze-Linux-on-Xilinx-ML605 Could you please tell me which steps in this manual dealt with "u-boot bsp"? I did not see u-boot mentioned anywhere in this manual, but I guess it is...
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    Questions about porting Linux OS on Microblaze with Virtex6 board

    I have a ML605 evaluation board. I have ISE13.4 on my Windows PC, and I installed ISE Webpack 14.7 on my Ubuntu laptop. What I want to do is to run a simple linux OS on microblaze. First, I use XPS and SDK on my Windoes PC to generate ise_top.bit and xilinx.dts. Then, I download a...
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    How do people usually store a Graph for VLSI routing?

    I am a beginner in the field of VLSI CAD. Now I have been working on some programming practice with Dijkstra's algorithm (find the shortest path in a graph). In such small project, I am simply using adjacency matrix to store the small toy graph. However, a friend of mine who is also a student...
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    Inquiry about size mismatch when importing GDSII to Virtuoso

    When generating the SRAM files with SRAM generator. The option "top metal layer : m5-m9" can not be changed. If the top metal layers are different from the metal layers supported by my Virtuoso folder, will it cause the above problem?
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    Inquiry about size mismatch when importing GDSII to Virtuoso

    I generated .gds2 and .vclef files with Artisan Physical IP (SRAM generator) from ARM. The exact size of the SRAM block was already known before I generated the above files. After I imported the .vclef file into virtuoso, I got an abstract (like a square layout without cells) of the correct...

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