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    [m]Is Output Voltage of the Synchronous Buck Converter independent of Load Resistance

    Hi all, A lot of online sources (ex: Wikipedia) give the input-output voltage relation of the Buck Converter as Vout = D . Vin; where, D is the duty cycle of the driving PWM signal. But is the Output voltage of the Synchronous Buck Converter independent of the Load Resistance ? What happens...
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    What is the source voltage of High side MOSFET in Buck Converter ?

    I am trying to model Buck Converter in Verilog. MOSFET model which I have designed has 3 inout ports - Source, Gate and Drain. During charging, High side MOSFET is ON, with the Inductor being charged. Drain terminal gets input voltage (12V) I have given PWM to the gate of MOSFET (When High side...
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    [SOLVED] Verilog implementation for d/dt time derivative

    Hello, I am trying to implement Capacitor and Inductor models in Verilog. These models have Voltage and Current equations which involve time derivative dI/dt and dV/dt. In Verilog AMS, we have a built-in function ddt(). But How do I implement these time derivative functions in Verilog ? Can...
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    Upper limit for sensitivity list elements in combinational block

    Hi all, Is there is any upper limit in the sensitivity list for a combinatorial always block..? For eg : If the combinatorial always block code is like : always @ (posedge a or posedge b or negedge c...) begin end My question is : Is there like only 2 elements must be present inside the...
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    Running tcl script with arguments

    Hi, I open a text file which is there in the testbench. I open it like this : initial begin fd = $fopen ("../testbench/includes/data.txt", "r"); end Now I will have to open and process different text file each time I run the simulation. So, instead of changing the text file in the...
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    Comparing text files in Verilog

    Hi All, Can anyone please tell me how to compare 2 text files in Verilog..? Thanks !

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