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  1. H

    Impact of surrounding logic - causes

    Hi, https://i.imgur.com/vsNsjOh.png suppose that I have an FPGA, and, based on the image above, that I have a circuit that is synthesized on the bottom-left part of the FPGA (green box). Furthermore, suppose that I synthesized another circuit (red box) that surrounds the first. This last...
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    Clock quality's influence on setup's times

    Hi, I'm searching for some material (papers, slides, books' chapters, etc.) that talks about the influence that the clock's quality has on setup's times and other timing charateristics. I've tried to search online, but I've not found much. I'd be very grateful if you could give me some...
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    FSM: Moore or Mealy?

    Hi, just a quick question... I have developed a FSM using VHDL and I'm questioning about if it is a Moore or a Mealy FSM. Here is the code: -- FSM states type state is (idle, init, init_shift, subtract, test, operation_sub1, operation_sub0, correction, finished); signal current_state...
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    Parallel stadium of Pipeline

    Hi, I have a Spartan-E3 FPGA and I'm realizing a (parallel) pipeline with 4 stages like this: https://i.imgur.com/6CQNk.png The two stages "T3" are the same. T1, T2 and T4 "run" at 50MHz, while T3 runs at 25MHz (and 180° shifted like in the figure). In Behavioral Simulation it works fine, the...
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    Maximum frequency on the board

    Hi, I realised the pipeline that I talked before (https://www.edaboard.com/threads/275809/), but now I have some doubts on the maximum frequency. I have a Spartan-3E FPGA running at 50MHz and I want to test my pipeline on it. I linked the output result with the 7-segments display and all works...
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    Pipeline - Multiplication problem

    Hi :) I have to realize a pipeline to execute this expression: (A+B)^2 - C[D - (E/2)] A, B, C, D and E are all signed 16 bit. However I can divide that operation into three (or four) stages: 1°: x=A+B and y=D-(E/2) (the division delay can be negligible because it's a simple right shift) 2°...
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    Undesiderated 1-bit latch

    Hi, I'm programming a N-bit non-restoring divider, but I faced a little problem. I have an Operative Part (combinatorial) and a Control Part (Finite State Machine). The Control Part has a 2 processes FSM, 1 for updating the next state and 1 for the "state sequence". update: process(clk_in...
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    Inconsistent Post-Route simulation (ISE)

    Hi, I created an 8bit Barrel Shifter and now I want to simulate it using Xilinx ISE tools, specifically I want to do a Post-Route simulation (the last step). I do these steps: 1. Synthesize - XST 2. Implement Design 3. I check the "Synthesis Report" and find: "Minimum period: 3.281ns (Maximum...
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    Connecting STD_LOGIC_VECTOR in different ways (Barrel Shifter)

    I am realizing a N-bit Barrel Shifter. Here it is my component: entity barrel_shifter is Generic ( N : integer := 4); Port ( data_in : in STD_LOGIC_VECTOR (N-1 downto 0); shift : in STD_LOGIC_VECTOR (integer(ceil(log2(real(N))))-1 downto 0); -- log2 of N => number of...
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    Generating a 78MHz clock from a 100MHz base clock

    I have to generate a 78MHz clock (duty cycle 0.5 or 0.7) from a 100MHz base clock (duty cycle 0.5) using VHDL language (so the ratio is 200/156). I know that I can use DCM, PLL or similar, but at this moment (unfortunately) I just can't. Therefore I thought to use (excluding any DCM or PLL) a...

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