Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
area utilization xilinx
what Aastik said is correct....and yes PnR tools does spread the logic a bit for timing but in your case the spreading does not seem to be more as LUT utilization is 95%....u could still add a liitle more logic if it does not affect your performance...then pnr will...
Re: CRC calculation
go to this website
it is a crc tool which generates VHDL or VERILOG code for any given CRC polynomial and any databus width...its FREE....and its the best
Re: cam in fpga
U cld do it using Dual port Block RAMS available in Xilinx FPGAS. it would take abt 6 such Dual port BRAMS to implement your CAM abt 200 - 300 slices and 3-4 clocks for the output result ..depending on your coding skills...refer to xilinx document on implementing CAM...XAPP260....
Re: Net List files
yes edn files are generated by xoregen....if u want to simulate then coregen also generates .vhd and .v files which r present in ur working directory... u can include these files in ur modelsim project and simulate if xilinx coregen libraries are complied in...
I need to connect at 72-bit wide block ram on a 32-bit wide data bus of microblaze...i think to achieve this in need to interface my bram with opb-ip i.e treat my Bram as an ip....but i still dont know how...as its the first time i'm going to implement microblaze...any ideas or docs are...
i have heard that python is good for RTL verification ....I know it is easy to learn...but before i go ahead can some one tell me whether it can be interfaced with modelsim and what is the verification flow to be followed or anyone have documents abt this pls....also it...
Re: need help about FPGA
here is a gud PDF...
Programmable Logic Design Quick Start Hand Book --Second edition
By Karen Parnell & Nick Mehta -- Xilinx
I also found an article on intermediate fpga in this forum which is gud.....i suggest tht u go through the article uploaded by me first and...
does anyone have documents or tutorials realting to VHDL design for area (FPGA) i.e efficient slice utilization coding or how the code infers Slices, LUTs, CLBS etc....i need to learn how to code so as to optimize for area.........
2**2 in vhdl
thanks for ur feedback...i did know abt n = a/(2^y) => (n = a >> y)....but i wanted to implement 16bit/16bit division.. denominator is a power of 2...in less than 20 slices...which was posing the problem...i was able to do it in 28 slices...if anyone can beat it its gud...